1137 lines
36 KiB
C
1137 lines
36 KiB
C
/*
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* ARM debug helpers.
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*
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* This code is licensed under the GNU GPL v2 or later.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "internals.h"
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#include "cpregs.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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/* Return the Exception Level targeted by debug exceptions. */
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static int arm_debug_target_el(CPUARMState *env)
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{
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bool secure = arm_is_secure(env);
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bool route_to_el2 = false;
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if (arm_is_el2_enabled(env)) {
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route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
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env->cp15.mdcr_el2 & MDCR_TDE;
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}
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if (route_to_el2) {
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return 2;
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} else if (arm_feature(env, ARM_FEATURE_EL3) &&
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!arm_el_is_aa64(env, 3) && secure) {
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return 3;
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} else {
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return 1;
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}
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}
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/*
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* Raise an exception to the debug target el.
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* Modify syndrome to indicate when origin and target EL are the same.
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*/
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G_NORETURN static void
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raise_exception_debug(CPUARMState *env, uint32_t excp, uint32_t syndrome)
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{
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int debug_el = arm_debug_target_el(env);
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int cur_el = arm_current_el(env);
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/*
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* If singlestep is targeting a lower EL than the current one, then
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* DisasContext.ss_active must be false and we can never get here.
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* Similarly for watchpoint and breakpoint matches.
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*/
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assert(debug_el >= cur_el);
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syndrome |= (debug_el == cur_el) << ARM_EL_EC_SHIFT;
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raise_exception(env, excp, syndrome, debug_el);
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}
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/* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */
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static bool aa64_generate_debug_exceptions(CPUARMState *env)
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{
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int cur_el = arm_current_el(env);
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int debug_el;
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if (cur_el == 3) {
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return false;
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}
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/* MDCR_EL3.SDD disables debug events from Secure state */
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if (arm_is_secure_below_el3(env)
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&& extract32(env->cp15.mdcr_el3, 16, 1)) {
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return false;
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}
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/*
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* Same EL to same EL debug exceptions need MDSCR_KDE enabled
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* while not masking the (D)ebug bit in DAIF.
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*/
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debug_el = arm_debug_target_el(env);
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if (cur_el == debug_el) {
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return extract32(env->cp15.mdscr_el1, 13, 1)
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&& !(env->daif & PSTATE_D);
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}
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/* Otherwise the debug target needs to be a higher EL */
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return debug_el > cur_el;
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}
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static bool aa32_generate_debug_exceptions(CPUARMState *env)
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{
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int el = arm_current_el(env);
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if (el == 0 && arm_el_is_aa64(env, 1)) {
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return aa64_generate_debug_exceptions(env);
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}
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if (arm_is_secure(env)) {
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int spd;
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if (el == 0 && (env->cp15.sder & 1)) {
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/*
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* SDER.SUIDEN means debug exceptions from Secure EL0
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* are always enabled. Otherwise they are controlled by
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* SDCR.SPD like those from other Secure ELs.
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*/
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return true;
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}
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spd = extract32(env->cp15.mdcr_el3, 14, 2);
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switch (spd) {
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case 1:
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/* SPD == 0b01 is reserved, but behaves as 0b00. */
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case 0:
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/*
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* For 0b00 we return true if external secure invasive debug
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* is enabled. On real hardware this is controlled by external
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* signals to the core. QEMU always permits debug, and behaves
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* as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high.
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*/
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return true;
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case 2:
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return false;
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case 3:
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return true;
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}
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}
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return el != 2;
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}
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/*
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* Return true if debugging exceptions are currently enabled.
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* This corresponds to what in ARM ARM pseudocode would be
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* if UsingAArch32() then
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* return AArch32.GenerateDebugExceptions()
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* else
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* return AArch64.GenerateDebugExceptions()
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* We choose to push the if() down into this function for clarity,
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* since the pseudocode has it at all callsites except for the one in
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* CheckSoftwareStep(), where it is elided because both branches would
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* always return the same value.
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*/
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bool arm_generate_debug_exceptions(CPUARMState *env)
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{
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if ((env->cp15.oslsr_el1 & 1) || (env->cp15.osdlr_el1 & 1)) {
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return false;
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}
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if (is_a64(env)) {
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return aa64_generate_debug_exceptions(env);
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} else {
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return aa32_generate_debug_exceptions(env);
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}
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}
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/*
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* Is single-stepping active? (Note that the "is EL_D AArch64?" check
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* implicitly means this always returns false in pre-v8 CPUs.)
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*/
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bool arm_singlestep_active(CPUARMState *env)
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{
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return extract32(env->cp15.mdscr_el1, 0, 1)
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&& arm_el_is_aa64(env, arm_debug_target_el(env))
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&& arm_generate_debug_exceptions(env);
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}
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/* Return true if the linked breakpoint entry lbn passes its checks */
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static bool linked_bp_matches(ARMCPU *cpu, int lbn)
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{
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CPUARMState *env = &cpu->env;
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uint64_t bcr = env->cp15.dbgbcr[lbn];
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int brps = arm_num_brps(cpu);
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int ctx_cmps = arm_num_ctx_cmps(cpu);
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int bt;
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uint32_t contextidr;
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uint64_t hcr_el2;
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/*
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* Links to unimplemented or non-context aware breakpoints are
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* CONSTRAINED UNPREDICTABLE: either behave as if disabled, or
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* as if linked to an UNKNOWN context-aware breakpoint (in which
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* case DBGWCR<n>_EL1.LBN must indicate that breakpoint).
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* We choose the former.
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*/
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if (lbn >= brps || lbn < (brps - ctx_cmps)) {
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return false;
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}
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bcr = env->cp15.dbgbcr[lbn];
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if (extract64(bcr, 0, 1) == 0) {
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/* Linked breakpoint disabled : generate no events */
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return false;
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}
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bt = extract64(bcr, 20, 4);
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hcr_el2 = arm_hcr_el2_eff(env);
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switch (bt) {
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case 3: /* linked context ID match */
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switch (arm_current_el(env)) {
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default:
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/* Context matches never fire in AArch64 EL3 */
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return false;
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case 2:
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if (!(hcr_el2 & HCR_E2H)) {
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/* Context matches never fire in EL2 without E2H enabled. */
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return false;
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}
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contextidr = env->cp15.contextidr_el[2];
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break;
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case 1:
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contextidr = env->cp15.contextidr_el[1];
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break;
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case 0:
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if ((hcr_el2 & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
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contextidr = env->cp15.contextidr_el[2];
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} else {
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contextidr = env->cp15.contextidr_el[1];
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}
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break;
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}
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break;
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case 7: /* linked contextidr_el1 match */
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contextidr = env->cp15.contextidr_el[1];
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break;
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case 13: /* linked contextidr_el2 match */
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contextidr = env->cp15.contextidr_el[2];
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break;
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case 9: /* linked VMID match (reserved if no EL2) */
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case 11: /* linked context ID and VMID match (reserved if no EL2) */
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case 15: /* linked full context ID match */
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default:
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/*
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* Links to Unlinked context breakpoints must generate no
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* events; we choose to do the same for reserved values too.
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*/
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return false;
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}
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/*
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* We match the whole register even if this is AArch32 using the
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* short descriptor format (in which case it holds both PROCID and ASID),
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* since we don't implement the optional v7 context ID masking.
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*/
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return contextidr == (uint32_t)env->cp15.dbgbvr[lbn];
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}
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static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
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{
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CPUARMState *env = &cpu->env;
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uint64_t cr;
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int pac, hmc, ssc, wt, lbn;
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/*
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* Note that for watchpoints the check is against the CPU security
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* state, not the S/NS attribute on the offending data access.
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*/
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bool is_secure = arm_is_secure(env);
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int access_el = arm_current_el(env);
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if (is_wp) {
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CPUWatchpoint *wp = env->cpu_watchpoint[n];
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if (!wp || !(wp->flags & BP_WATCHPOINT_HIT)) {
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return false;
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}
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cr = env->cp15.dbgwcr[n];
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if (wp->hitattrs.user) {
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/*
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* The LDRT/STRT/LDT/STT "unprivileged access" instructions should
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* match watchpoints as if they were accesses done at EL0, even if
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* the CPU is at EL1 or higher.
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*/
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access_el = 0;
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}
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} else {
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uint64_t pc = is_a64(env) ? env->pc : env->regs[15];
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if (!env->cpu_breakpoint[n] || env->cpu_breakpoint[n]->pc != pc) {
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return false;
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}
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cr = env->cp15.dbgbcr[n];
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}
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/*
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* The WATCHPOINT_HIT flag guarantees us that the watchpoint is
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* enabled and that the address and access type match; for breakpoints
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* we know the address matched; check the remaining fields, including
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* linked breakpoints. We rely on WCR and BCR having the same layout
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* for the LBN, SSC, HMC, PAC/PMC and is-linked fields.
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* Note that some combinations of {PAC, HMC, SSC} are reserved and
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* must act either like some valid combination or as if the watchpoint
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* were disabled. We choose the former, and use this together with
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* the fact that EL3 must always be Secure and EL2 must always be
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* Non-Secure to simplify the code slightly compared to the full
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* table in the ARM ARM.
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*/
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pac = FIELD_EX64(cr, DBGWCR, PAC);
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hmc = FIELD_EX64(cr, DBGWCR, HMC);
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ssc = FIELD_EX64(cr, DBGWCR, SSC);
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switch (ssc) {
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case 0:
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break;
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case 1:
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case 3:
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if (is_secure) {
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return false;
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}
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break;
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case 2:
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if (!is_secure) {
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return false;
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}
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break;
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}
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switch (access_el) {
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case 3:
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case 2:
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if (!hmc) {
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return false;
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}
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break;
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case 1:
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if (extract32(pac, 0, 1) == 0) {
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return false;
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}
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break;
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case 0:
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if (extract32(pac, 1, 1) == 0) {
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return false;
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}
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break;
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default:
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g_assert_not_reached();
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}
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wt = FIELD_EX64(cr, DBGWCR, WT);
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lbn = FIELD_EX64(cr, DBGWCR, LBN);
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if (wt && !linked_bp_matches(cpu, lbn)) {
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return false;
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}
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return true;
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}
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static bool check_watchpoints(ARMCPU *cpu)
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{
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CPUARMState *env = &cpu->env;
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int n;
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/*
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* If watchpoints are disabled globally or we can't take debug
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* exceptions here then watchpoint firings are ignored.
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*/
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if (extract32(env->cp15.mdscr_el1, 15, 1) == 0
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|| !arm_generate_debug_exceptions(env)) {
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return false;
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}
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for (n = 0; n < ARRAY_SIZE(env->cpu_watchpoint); n++) {
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if (bp_wp_matches(cpu, n, true)) {
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return true;
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}
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}
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return false;
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}
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bool arm_debug_check_breakpoint(CPUState *cs)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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target_ulong pc;
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int n;
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/*
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* If breakpoints are disabled globally or we can't take debug
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* exceptions here then breakpoint firings are ignored.
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*/
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if (extract32(env->cp15.mdscr_el1, 15, 1) == 0
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|| !arm_generate_debug_exceptions(env)) {
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return false;
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}
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/*
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* Single-step exceptions have priority over breakpoint exceptions.
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* If single-step state is active-pending, suppress the bp.
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*/
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if (arm_singlestep_active(env) && !(env->pstate & PSTATE_SS)) {
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return false;
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}
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/*
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* PC alignment faults have priority over breakpoint exceptions.
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*/
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pc = is_a64(env) ? env->pc : env->regs[15];
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if ((is_a64(env) || !env->thumb) && (pc & 3) != 0) {
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return false;
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}
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/*
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* Instruction aborts have priority over breakpoint exceptions.
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* TODO: We would need to look up the page for PC and verify that
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* it is present and executable.
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*/
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for (n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) {
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if (bp_wp_matches(cpu, n, false)) {
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return true;
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}
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}
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return false;
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}
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bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
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{
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/*
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* Called by core code when a CPU watchpoint fires; need to check if this
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* is also an architectural watchpoint match.
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*/
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ARMCPU *cpu = ARM_CPU(cs);
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return check_watchpoints(cpu);
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}
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/*
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* Return the FSR value for a debug exception (watchpoint, hardware
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* breakpoint or BKPT insn) targeting the specified exception level.
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*/
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static uint32_t arm_debug_exception_fsr(CPUARMState *env)
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{
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ARMMMUFaultInfo fi = { .type = ARMFault_Debug };
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int target_el = arm_debug_target_el(env);
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bool using_lpae = false;
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if (target_el == 2 || arm_el_is_aa64(env, target_el)) {
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using_lpae = true;
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} else {
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if (arm_feature(env, ARM_FEATURE_LPAE) &&
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(env->cp15.tcr_el[target_el] & TTBCR_EAE)) {
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using_lpae = true;
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}
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}
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if (using_lpae) {
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return arm_fi_to_lfsc(&fi);
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} else {
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return arm_fi_to_sfsc(&fi);
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}
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}
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void arm_debug_excp_handler(CPUState *cs)
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{
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/*
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* Called by core code when a watchpoint or breakpoint fires;
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* need to check which one and raise the appropriate exception.
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*/
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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CPUWatchpoint *wp_hit = cs->watchpoint_hit;
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if (wp_hit) {
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if (wp_hit->flags & BP_CPU) {
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bool wnr = (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) != 0;
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cs->watchpoint_hit = NULL;
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env->exception.fsr = arm_debug_exception_fsr(env);
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env->exception.vaddress = wp_hit->hitaddr;
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raise_exception_debug(env, EXCP_DATA_ABORT,
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syn_watchpoint(0, 0, wnr));
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}
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} else {
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uint64_t pc = is_a64(env) ? env->pc : env->regs[15];
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|
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/*
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* (1) GDB breakpoints should be handled first.
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* (2) Do not raise a CPU exception if no CPU breakpoint has fired,
|
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* since singlestep is also done by generating a debug internal
|
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* exception.
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*/
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if (cpu_breakpoint_test(cs, pc, BP_GDB)
|
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|| !cpu_breakpoint_test(cs, pc, BP_CPU)) {
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return;
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}
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|
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env->exception.fsr = arm_debug_exception_fsr(env);
|
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/*
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* FAR is UNKNOWN: clear vaddress to avoid potentially exposing
|
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* values to the guest that it shouldn't be able to see at its
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* exception/security level.
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*/
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env->exception.vaddress = 0;
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raise_exception_debug(env, EXCP_PREFETCH_ABORT, syn_breakpoint(0));
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}
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}
|
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|
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/*
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* Raise an EXCP_BKPT with the specified syndrome register value,
|
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* targeting the correct exception level for debug exceptions.
|
|
*/
|
|
void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome)
|
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{
|
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int debug_el = arm_debug_target_el(env);
|
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int cur_el = arm_current_el(env);
|
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|
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/* FSR will only be used if the debug target EL is AArch32. */
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env->exception.fsr = arm_debug_exception_fsr(env);
|
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/*
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* FAR is UNKNOWN: clear vaddress to avoid potentially exposing
|
|
* values to the guest that it shouldn't be able to see at its
|
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* exception/security level.
|
|
*/
|
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env->exception.vaddress = 0;
|
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/*
|
|
* Other kinds of architectural debug exception are ignored if
|
|
* they target an exception level below the current one (in QEMU
|
|
* this is checked by arm_generate_debug_exceptions()). Breakpoint
|
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* instructions are special because they always generate an exception
|
|
* to somewhere: if they can't go to the configured debug exception
|
|
* level they are taken to the current exception level.
|
|
*/
|
|
if (debug_el < cur_el) {
|
|
debug_el = cur_el;
|
|
}
|
|
raise_exception(env, EXCP_BKPT, syndrome, debug_el);
|
|
}
|
|
|
|
void HELPER(exception_swstep)(CPUARMState *env, uint32_t syndrome)
|
|
{
|
|
raise_exception_debug(env, EXCP_UDEF, syndrome);
|
|
}
|
|
|
|
/*
|
|
* Check for traps to "powerdown debug" registers, which are controlled
|
|
* by MDCR.TDOSA
|
|
*/
|
|
static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri,
|
|
bool isread)
|
|
{
|
|
int el = arm_current_el(env);
|
|
uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
|
|
bool mdcr_el2_tdosa = (mdcr_el2 & MDCR_TDOSA) || (mdcr_el2 & MDCR_TDE) ||
|
|
(arm_hcr_el2_eff(env) & HCR_TGE);
|
|
|
|
if (el < 2 && mdcr_el2_tdosa) {
|
|
return CP_ACCESS_TRAP_EL2;
|
|
}
|
|
if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) {
|
|
return CP_ACCESS_TRAP_EL3;
|
|
}
|
|
return CP_ACCESS_OK;
|
|
}
|
|
|
|
/*
|
|
* Check for traps to "debug ROM" registers, which are controlled
|
|
* by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
|
|
*/
|
|
static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri,
|
|
bool isread)
|
|
{
|
|
int el = arm_current_el(env);
|
|
uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
|
|
bool mdcr_el2_tdra = (mdcr_el2 & MDCR_TDRA) || (mdcr_el2 & MDCR_TDE) ||
|
|
(arm_hcr_el2_eff(env) & HCR_TGE);
|
|
|
|
if (el < 2 && mdcr_el2_tdra) {
|
|
return CP_ACCESS_TRAP_EL2;
|
|
}
|
|
if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
|
|
return CP_ACCESS_TRAP_EL3;
|
|
}
|
|
return CP_ACCESS_OK;
|
|
}
|
|
|
|
/*
|
|
* Check for traps to general debug registers, which are controlled
|
|
* by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
|
|
*/
|
|
static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri,
|
|
bool isread)
|
|
{
|
|
int el = arm_current_el(env);
|
|
uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
|
|
bool mdcr_el2_tda = (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) ||
|
|
(arm_hcr_el2_eff(env) & HCR_TGE);
|
|
|
|
if (el < 2 && mdcr_el2_tda) {
|
|
return CP_ACCESS_TRAP_EL2;
|
|
}
|
|
if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
|
|
return CP_ACCESS_TRAP_EL3;
|
|
}
|
|
return CP_ACCESS_OK;
|
|
}
|
|
|
|
static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
|
uint64_t value)
|
|
{
|
|
/*
|
|
* Writes to OSLAR_EL1 may update the OS lock status, which can be
|
|
* read via a bit in OSLSR_EL1.
|
|
*/
|
|
int oslock;
|
|
|
|
if (ri->state == ARM_CP_STATE_AA32) {
|
|
oslock = (value == 0xC5ACCE55);
|
|
} else {
|
|
oslock = value & 1;
|
|
}
|
|
|
|
env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock);
|
|
}
|
|
|
|
static void osdlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
|
uint64_t value)
|
|
{
|
|
ARMCPU *cpu = env_archcpu(env);
|
|
/*
|
|
* Only defined bit is bit 0 (DLK); if Feat_DoubleLock is not
|
|
* implemented this is RAZ/WI.
|
|
*/
|
|
if(arm_feature(env, ARM_FEATURE_AARCH64)
|
|
? cpu_isar_feature(aa64_doublelock, cpu)
|
|
: cpu_isar_feature(aa32_doublelock, cpu)) {
|
|
env->cp15.osdlr_el1 = value & 1;
|
|
}
|
|
}
|
|
|
|
static const ARMCPRegInfo debug_cp_reginfo[] = {
|
|
/*
|
|
* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
|
|
* debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
|
|
* unlike DBGDRAR it is never accessible from EL0.
|
|
* DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
|
|
* accessor.
|
|
*/
|
|
{ .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
|
|
.access = PL0_R, .accessfn = access_tdra,
|
|
.type = ARM_CP_CONST, .resetvalue = 0 },
|
|
{ .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
|
|
.opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
|
|
.access = PL1_R, .accessfn = access_tdra,
|
|
.type = ARM_CP_CONST, .resetvalue = 0 },
|
|
{ .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
|
|
.access = PL0_R, .accessfn = access_tdra,
|
|
.type = ARM_CP_CONST, .resetvalue = 0 },
|
|
/* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
|
|
{ .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
|
|
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
|
|
.access = PL1_RW, .accessfn = access_tda,
|
|
.fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
|
|
.resetvalue = 0 },
|
|
/*
|
|
* MDCCSR_EL0[30:29] map to EDSCR[30:29]. Simply RAZ as the external
|
|
* Debug Communication Channel is not implemented.
|
|
*/
|
|
{ .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64,
|
|
.opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
|
|
.access = PL0_R, .accessfn = access_tda,
|
|
.type = ARM_CP_CONST, .resetvalue = 0 },
|
|
/*
|
|
* DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as
|
|
* it is unlikely a guest will care.
|
|
* We don't implement the configurable EL0 access.
|
|
*/
|
|
{ .name = "DBGDSCRint", .state = ARM_CP_STATE_AA32,
|
|
.cp = 14, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
|
|
.type = ARM_CP_ALIAS,
|
|
.access = PL1_R, .accessfn = access_tda,
|
|
.fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
|
|
{ .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
|
|
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
|
|
.access = PL1_W, .type = ARM_CP_NO_RAW,
|
|
.accessfn = access_tdosa,
|
|
.writefn = oslar_write },
|
|
{ .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH,
|
|
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4,
|
|
.access = PL1_R, .resetvalue = 10,
|
|
.accessfn = access_tdosa,
|
|
.fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) },
|
|
/* Dummy OSDLR_EL1: 32-bit Linux will read this */
|
|
{ .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
|
|
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
|
|
.access = PL1_RW, .accessfn = access_tdosa,
|
|
.writefn = osdlr_write,
|
|
.fieldoffset = offsetof(CPUARMState, cp15.osdlr_el1) },
|
|
/*
|
|
* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
|
|
* implement vector catch debug events yet.
|
|
*/
|
|
{ .name = "DBGVCR",
|
|
.cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
|
|
.access = PL1_RW, .accessfn = access_tda,
|
|
.type = ARM_CP_NOP },
|
|
/*
|
|
* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
|
|
* to save and restore a 32-bit guest's DBGVCR)
|
|
*/
|
|
{ .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
|
|
.opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
|
|
.access = PL2_RW, .accessfn = access_tda,
|
|
.type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP },
|
|
/*
|
|
* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
|
|
* Channel but Linux may try to access this register. The 32-bit
|
|
* alias is DBGDCCINT.
|
|
*/
|
|
{ .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
|
|
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
|
|
.access = PL1_RW, .accessfn = access_tda,
|
|
.type = ARM_CP_NOP },
|
|
};
|
|
|
|
static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
|
|
/* 64 bit access versions of the (dummy) debug registers */
|
|
{ .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
|
|
.access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
|
|
{ .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
|
|
.access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
|
|
};
|
|
|
|
void hw_watchpoint_update(ARMCPU *cpu, int n)
|
|
{
|
|
CPUARMState *env = &cpu->env;
|
|
vaddr len = 0;
|
|
vaddr wvr = env->cp15.dbgwvr[n];
|
|
uint64_t wcr = env->cp15.dbgwcr[n];
|
|
int mask;
|
|
int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
|
|
|
|
if (env->cpu_watchpoint[n]) {
|
|
cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
|
|
env->cpu_watchpoint[n] = NULL;
|
|
}
|
|
|
|
if (!FIELD_EX64(wcr, DBGWCR, E)) {
|
|
/* E bit clear : watchpoint disabled */
|
|
return;
|
|
}
|
|
|
|
switch (FIELD_EX64(wcr, DBGWCR, LSC)) {
|
|
case 0:
|
|
/* LSC 00 is reserved and must behave as if the wp is disabled */
|
|
return;
|
|
case 1:
|
|
flags |= BP_MEM_READ;
|
|
break;
|
|
case 2:
|
|
flags |= BP_MEM_WRITE;
|
|
break;
|
|
case 3:
|
|
flags |= BP_MEM_ACCESS;
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* Attempts to use both MASK and BAS fields simultaneously are
|
|
* CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
|
|
* thus generating a watchpoint for every byte in the masked region.
|
|
*/
|
|
mask = FIELD_EX64(wcr, DBGWCR, MASK);
|
|
if (mask == 1 || mask == 2) {
|
|
/*
|
|
* Reserved values of MASK; we must act as if the mask value was
|
|
* some non-reserved value, or as if the watchpoint were disabled.
|
|
* We choose the latter.
|
|
*/
|
|
return;
|
|
} else if (mask) {
|
|
/* Watchpoint covers an aligned area up to 2GB in size */
|
|
len = 1ULL << mask;
|
|
/*
|
|
* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
|
|
* whether the watchpoint fires when the unmasked bits match; we opt
|
|
* to generate the exceptions.
|
|
*/
|
|
wvr &= ~(len - 1);
|
|
} else {
|
|
/* Watchpoint covers bytes defined by the byte address select bits */
|
|
int bas = FIELD_EX64(wcr, DBGWCR, BAS);
|
|
int basstart;
|
|
|
|
if (extract64(wvr, 2, 1)) {
|
|
/*
|
|
* Deprecated case of an only 4-aligned address. BAS[7:4] are
|
|
* ignored, and BAS[3:0] define which bytes to watch.
|
|
*/
|
|
bas &= 0xf;
|
|
}
|
|
|
|
if (bas == 0) {
|
|
/* This must act as if the watchpoint is disabled */
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* The BAS bits are supposed to be programmed to indicate a contiguous
|
|
* range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
|
|
* we fire for each byte in the word/doubleword addressed by the WVR.
|
|
* We choose to ignore any non-zero bits after the first range of 1s.
|
|
*/
|
|
basstart = ctz32(bas);
|
|
len = cto32(bas >> basstart);
|
|
wvr += basstart;
|
|
}
|
|
|
|
cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
|
|
&env->cpu_watchpoint[n]);
|
|
}
|
|
|
|
void hw_watchpoint_update_all(ARMCPU *cpu)
|
|
{
|
|
int i;
|
|
CPUARMState *env = &cpu->env;
|
|
|
|
/*
|
|
* Completely clear out existing QEMU watchpoints and our array, to
|
|
* avoid possible stale entries following migration load.
|
|
*/
|
|
cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
|
|
memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
|
|
|
|
for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
|
|
hw_watchpoint_update(cpu, i);
|
|
}
|
|
}
|
|
|
|
static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
|
uint64_t value)
|
|
{
|
|
ARMCPU *cpu = env_archcpu(env);
|
|
int i = ri->crm;
|
|
|
|
/*
|
|
* Bits [1:0] are RES0.
|
|
*
|
|
* It is IMPLEMENTATION DEFINED whether [63:49] ([63:53] with FEAT_LVA)
|
|
* are hardwired to the value of bit [48] ([52] with FEAT_LVA), or if
|
|
* they contain the value written. It is CONSTRAINED UNPREDICTABLE
|
|
* whether the RESS bits are ignored when comparing an address.
|
|
*
|
|
* Therefore we are allowed to compare the entire register, which lets
|
|
* us avoid considering whether or not FEAT_LVA is actually enabled.
|
|
*/
|
|
value &= ~3ULL;
|
|
|
|
raw_write(env, ri, value);
|
|
hw_watchpoint_update(cpu, i);
|
|
}
|
|
|
|
static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
|
uint64_t value)
|
|
{
|
|
ARMCPU *cpu = env_archcpu(env);
|
|
int i = ri->crm;
|
|
|
|
raw_write(env, ri, value);
|
|
hw_watchpoint_update(cpu, i);
|
|
}
|
|
|
|
void hw_breakpoint_update(ARMCPU *cpu, int n)
|
|
{
|
|
CPUARMState *env = &cpu->env;
|
|
uint64_t bvr = env->cp15.dbgbvr[n];
|
|
uint64_t bcr = env->cp15.dbgbcr[n];
|
|
vaddr addr;
|
|
int bt;
|
|
int flags = BP_CPU;
|
|
|
|
if (env->cpu_breakpoint[n]) {
|
|
cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
|
|
env->cpu_breakpoint[n] = NULL;
|
|
}
|
|
|
|
if (!extract64(bcr, 0, 1)) {
|
|
/* E bit clear : watchpoint disabled */
|
|
return;
|
|
}
|
|
|
|
bt = extract64(bcr, 20, 4);
|
|
|
|
switch (bt) {
|
|
case 4: /* unlinked address mismatch (reserved if AArch64) */
|
|
case 5: /* linked address mismatch (reserved if AArch64) */
|
|
qemu_log_mask(LOG_UNIMP,
|
|
"arm: address mismatch breakpoint types not implemented\n");
|
|
return;
|
|
case 0: /* unlinked address match */
|
|
case 1: /* linked address match */
|
|
{
|
|
/*
|
|
* Bits [1:0] are RES0.
|
|
*
|
|
* It is IMPLEMENTATION DEFINED whether bits [63:49]
|
|
* ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit
|
|
* of the VA field ([48] or [52] for FEAT_LVA), or whether the
|
|
* value is read as written. It is CONSTRAINED UNPREDICTABLE
|
|
* whether the RESS bits are ignored when comparing an address.
|
|
* Therefore we are allowed to compare the entire register, which
|
|
* lets us avoid considering whether FEAT_LVA is actually enabled.
|
|
*
|
|
* The BAS field is used to allow setting breakpoints on 16-bit
|
|
* wide instructions; it is CONSTRAINED UNPREDICTABLE whether
|
|
* a bp will fire if the addresses covered by the bp and the addresses
|
|
* covered by the insn overlap but the insn doesn't start at the
|
|
* start of the bp address range. We choose to require the insn and
|
|
* the bp to have the same address. The constraints on writing to
|
|
* BAS enforced in dbgbcr_write mean we have only four cases:
|
|
* 0b0000 => no breakpoint
|
|
* 0b0011 => breakpoint on addr
|
|
* 0b1100 => breakpoint on addr + 2
|
|
* 0b1111 => breakpoint on addr
|
|
* See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
|
|
*/
|
|
int bas = extract64(bcr, 5, 4);
|
|
addr = bvr & ~3ULL;
|
|
if (bas == 0) {
|
|
return;
|
|
}
|
|
if (bas == 0xc) {
|
|
addr += 2;
|
|
}
|
|
break;
|
|
}
|
|
case 2: /* unlinked context ID match */
|
|
case 8: /* unlinked VMID match (reserved if no EL2) */
|
|
case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
|
|
qemu_log_mask(LOG_UNIMP,
|
|
"arm: unlinked context breakpoint types not implemented\n");
|
|
return;
|
|
case 9: /* linked VMID match (reserved if no EL2) */
|
|
case 11: /* linked context ID and VMID match (reserved if no EL2) */
|
|
case 3: /* linked context ID match */
|
|
default:
|
|
/*
|
|
* We must generate no events for Linked context matches (unless
|
|
* they are linked to by some other bp/wp, which is handled in
|
|
* updates for the linking bp/wp). We choose to also generate no events
|
|
* for reserved values.
|
|
*/
|
|
return;
|
|
}
|
|
|
|
cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
|
|
}
|
|
|
|
void hw_breakpoint_update_all(ARMCPU *cpu)
|
|
{
|
|
int i;
|
|
CPUARMState *env = &cpu->env;
|
|
|
|
/*
|
|
* Completely clear out existing QEMU breakpoints and our array, to
|
|
* avoid possible stale entries following migration load.
|
|
*/
|
|
cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
|
|
memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
|
|
|
|
for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
|
|
hw_breakpoint_update(cpu, i);
|
|
}
|
|
}
|
|
|
|
static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
|
uint64_t value)
|
|
{
|
|
ARMCPU *cpu = env_archcpu(env);
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|
int i = ri->crm;
|
|
|
|
raw_write(env, ri, value);
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|
hw_breakpoint_update(cpu, i);
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|
}
|
|
|
|
static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
|
uint64_t value)
|
|
{
|
|
ARMCPU *cpu = env_archcpu(env);
|
|
int i = ri->crm;
|
|
|
|
/*
|
|
* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
|
|
* copy of BAS[0].
|
|
*/
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|
value = deposit64(value, 6, 1, extract64(value, 5, 1));
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|
value = deposit64(value, 8, 1, extract64(value, 7, 1));
|
|
|
|
raw_write(env, ri, value);
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|
hw_breakpoint_update(cpu, i);
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|
}
|
|
|
|
void define_debug_regs(ARMCPU *cpu)
|
|
{
|
|
/*
|
|
* Define v7 and v8 architectural debug registers.
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|
* These are just dummy implementations for now.
|
|
*/
|
|
int i;
|
|
int wrps, brps, ctx_cmps;
|
|
|
|
/*
|
|
* The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot
|
|
* use AArch32. Given that bit 15 is RES1, if the value is 0 then
|
|
* the register must not exist for this cpu.
|
|
*/
|
|
if (cpu->isar.dbgdidr != 0) {
|
|
ARMCPRegInfo dbgdidr = {
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|
.name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0,
|
|
.opc1 = 0, .opc2 = 0,
|
|
.access = PL0_R, .accessfn = access_tda,
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|
.type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr,
|
|
};
|
|
define_one_arm_cp_reg(cpu, &dbgdidr);
|
|
}
|
|
|
|
/*
|
|
* DBGDEVID is present in the v7 debug architecture if
|
|
* DBGDIDR.DEVID_imp is 1 (bit 15); from v7.1 and on it is
|
|
* mandatory (and bit 15 is RES1). DBGDEVID1 and DBGDEVID2 exist
|
|
* from v7.1 of the debug architecture. Because no fields have yet
|
|
* been defined in DBGDEVID2 (and quite possibly none will ever
|
|
* be) we don't define an ARMISARegisters field for it.
|
|
* These registers exist only if EL1 can use AArch32, but that
|
|
* happens naturally because they are only PL1 accessible anyway.
|
|
*/
|
|
if (extract32(cpu->isar.dbgdidr, 15, 1)) {
|
|
ARMCPRegInfo dbgdevid = {
|
|
.name = "DBGDEVID",
|
|
.cp = 14, .opc1 = 0, .crn = 7, .opc2 = 2, .crn = 7,
|
|
.access = PL1_R, .accessfn = access_tda,
|
|
.type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdevid,
|
|
};
|
|
define_one_arm_cp_reg(cpu, &dbgdevid);
|
|
}
|
|
if (cpu_isar_feature(aa32_debugv7p1, cpu)) {
|
|
ARMCPRegInfo dbgdevid12[] = {
|
|
{
|
|
.name = "DBGDEVID1",
|
|
.cp = 14, .opc1 = 0, .crn = 7, .opc2 = 1, .crn = 7,
|
|
.access = PL1_R, .accessfn = access_tda,
|
|
.type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdevid1,
|
|
}, {
|
|
.name = "DBGDEVID2",
|
|
.cp = 14, .opc1 = 0, .crn = 7, .opc2 = 0, .crn = 7,
|
|
.access = PL1_R, .accessfn = access_tda,
|
|
.type = ARM_CP_CONST, .resetvalue = 0,
|
|
},
|
|
};
|
|
define_arm_cp_regs(cpu, dbgdevid12);
|
|
}
|
|
|
|
brps = arm_num_brps(cpu);
|
|
wrps = arm_num_wrps(cpu);
|
|
ctx_cmps = arm_num_ctx_cmps(cpu);
|
|
|
|
assert(ctx_cmps <= brps);
|
|
|
|
define_arm_cp_regs(cpu, debug_cp_reginfo);
|
|
|
|
if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
|
|
define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
|
|
}
|
|
|
|
for (i = 0; i < brps; i++) {
|
|
char *dbgbvr_el1_name = g_strdup_printf("DBGBVR%d_EL1", i);
|
|
char *dbgbcr_el1_name = g_strdup_printf("DBGBCR%d_EL1", i);
|
|
ARMCPRegInfo dbgregs[] = {
|
|
{ .name = dbgbvr_el1_name, .state = ARM_CP_STATE_BOTH,
|
|
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
|
|
.access = PL1_RW, .accessfn = access_tda,
|
|
.fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
|
|
.writefn = dbgbvr_write, .raw_writefn = raw_write
|
|
},
|
|
{ .name = dbgbcr_el1_name, .state = ARM_CP_STATE_BOTH,
|
|
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
|
|
.access = PL1_RW, .accessfn = access_tda,
|
|
.fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
|
|
.writefn = dbgbcr_write, .raw_writefn = raw_write
|
|
},
|
|
};
|
|
define_arm_cp_regs(cpu, dbgregs);
|
|
g_free(dbgbvr_el1_name);
|
|
g_free(dbgbcr_el1_name);
|
|
}
|
|
|
|
for (i = 0; i < wrps; i++) {
|
|
char *dbgwvr_el1_name = g_strdup_printf("DBGWVR%d_EL1", i);
|
|
char *dbgwcr_el1_name = g_strdup_printf("DBGWCR%d_EL1", i);
|
|
ARMCPRegInfo dbgregs[] = {
|
|
{ .name = dbgwvr_el1_name, .state = ARM_CP_STATE_BOTH,
|
|
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
|
|
.access = PL1_RW, .accessfn = access_tda,
|
|
.fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
|
|
.writefn = dbgwvr_write, .raw_writefn = raw_write
|
|
},
|
|
{ .name = dbgwcr_el1_name, .state = ARM_CP_STATE_BOTH,
|
|
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
|
|
.access = PL1_RW, .accessfn = access_tda,
|
|
.fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
|
|
.writefn = dbgwcr_write, .raw_writefn = raw_write
|
|
},
|
|
};
|
|
define_arm_cp_regs(cpu, dbgregs);
|
|
g_free(dbgwvr_el1_name);
|
|
g_free(dbgwcr_el1_name);
|
|
}
|
|
}
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(cs);
|
|
CPUARMState *env = &cpu->env;
|
|
|
|
/*
|
|
* In BE32 system mode, target memory is stored byteswapped (on a
|
|
* little-endian host system), and by the time we reach here (via an
|
|
* opcode helper) the addresses of subword accesses have been adjusted
|
|
* to account for that, which means that watchpoints will not match.
|
|
* Undo the adjustment here.
|
|
*/
|
|
if (arm_sctlr_b(env)) {
|
|
if (len == 1) {
|
|
addr ^= 3;
|
|
} else if (len == 2) {
|
|
addr ^= 2;
|
|
}
|
|
}
|
|
|
|
return addr;
|
|
}
|
|
|
|
#endif
|