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d4cad54499
qemu-e2k/hw/riscv
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Alistair Francis d4cad54499 hw/opentitan: Update the interrupt layout 
Update the OpenTitan interrupt layout to match the latest OpenTitan
bitstreams. This involves changing the Ibex PLIC memory layout and the
UART interrupts.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: e92b696f1809c9fa4410da2e9f23c414db5a6960.1617202791.git.alistair.francis@wdc.com
2021-05-11 20:02:06 +10:00
..
boot.c riscv: Pass RISCVHartArrayState by pointer 2021-01-16 14:34:46 -08:00
Kconfig riscv: Add initial support for Shakti C machine 2021-05-11 20:01:38 +10:00
meson.build riscv: Add initial support for Shakti C machine 2021-05-11 20:01:38 +10:00
microchip_pfsoc.c hw: Do not include qemu/log.h if it is not necessary 2021-05-02 17:24:50 +02:00
numa.c hw: Do not include qemu/log.h if it is not necessary 2021-05-02 17:24:50 +02:00
opentitan.c hw/opentitan: Update the interrupt layout 2021-05-11 20:02:06 +10:00
riscv_hart.c hw/riscv: hart: Add a new 'resetvec' property 2020-09-09 15:54:18 -07:00
shakti_c.c hw/riscv: Connect Shakti UART to Shakti platform 2021-05-11 20:02:06 +10:00
sifive_e.c hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[] 2021-05-11 20:01:10 +10:00
sifive_u.c hw: Do not include qemu/log.h if it is not necessary 2021-05-02 17:24:50 +02:00
spike.c hw: Do not include qemu/log.h if it is not necessary 2021-05-02 17:24:50 +02:00
virt.c hw: Do not include qemu/log.h if it is not necessary 2021-05-02 17:24:50 +02:00