Yongbok Kim ca1ffd14ed target/mips: Add I6500 core configuration ... Add I6500 core configuration. Note that this configuration is supported only on best-effort basis due to the lack of certain features in QEMU. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>		2019-01-24 17:48:33 +01:00
..
cp0_timer.c
cpu-qom.h
cpu.c
cpu.h	target/mips: Correct the second argument type of cpu_supports_isa()	2019-01-24 17:48:33 +01:00
dsp_helper.c
gdbstub.c
helper.c
helper.h	target/mips: Provide R/W access to SAARI and SAAR CP0 registers	2019-01-18 16:53:28 +01:00
internal.h	target/mips: Provide R/W access to SAARI and SAAR CP0 registers	2019-01-18 16:53:28 +01:00
kvm_mips.h
kvm.c
lmi_helper.c
machine.c	target/mips: Add CP0 register MemoryMapID	2019-01-18 16:53:28 +01:00
Makefile.objs
mips-defs.h
mips-semi.c
msa_helper.c
op_helper.c	target/mips: Update ITU to utilize SAARI and SAAR CP0 registers	2019-01-18 16:53:28 +01:00
TODO
trace-events
translate_init.inc.c	target/mips: Add I6500 core configuration	2019-01-24 17:48:33 +01:00
translate.c	target/mips: nanoMIPS: Fix branch handling	2019-01-24 17:48:33 +01:00