Matheus Ferst 9193eaa901 target/ppc: Implement Vector Mask Move insns ... Implement the following PowerISA v3.1 instructions: mtvsrbm: Move to VSR Byte Mask mtvsrhm: Move to VSR Halfword Mask mtvsrwm: Move to VSR Word Mask mtvsrdm: Move to VSR Doubleword Mask mtvsrqm: Move to VSR Quadword Mask mtvsrbmi: Move to VSR Byte Mask Immediate Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20211203194229.746275-4-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>		2021-12-17 17:57:13 +01:00
..
alpha
arm	Revert "arm: tcg: Adhere to SMCCC 1.3 section 5.2"	2021-11-22 13:41:48 +00:00
avr
cris
hexagon
hppa
i386	Bugfixes for 6.2.	2021-11-19 17:16:57 +01:00
m68k
microblaze
mips
nios2
openrisc
ppc	target/ppc: Implement Vector Mask Move insns	2021-12-17 17:57:13 +01:00
riscv	target/riscv: machine: Sort the .subsections	2021-11-17 19:18:22 +10:00
rx
s390x	target/s390x/cpu.h: Remove unused SIGP_MODE defines	2021-11-17 10:17:28 +01:00
sh4
sparc
tricore
xtensa
Kconfig
meson.build