adacc814f5
This commit enables each CXL Type-3 device to contain one volatile memory region and one persistent region. Two new properties have been added to cxl-type3 device initialization: [volatile-memdev] and [persistent-memdev] The existing [memdev] property has been deprecated and will default the memory region to a persistent memory region (although a user may assign the region to a ram or file backed region). It cannot be used in combination with the new [persistent-memdev] property. Partitioning volatile memory from persistent memory is not yet supported. Volatile memory is mapped at DPA(0x0), while Persistent memory is mapped at DPA(vmem->size), per CXL Spec 8.2.9.8.2.0 - Get Partition Info. Signed-off-by: Gregory Price <gregory.price@memverge.com> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net> Reviewed-by: Fan Ni <fan.ni@samsung.com> Tested-by: Fan Ni <fan.ni@samsung.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230421160827.2227-4-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
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_templates | ||
about | ||
config | ||
devel | ||
interop | ||
specs | ||
sphinx | ||
sphinx-static | ||
spin | ||
system | ||
tools | ||
user | ||
block-replication.txt | ||
bypass-iommu.txt | ||
COLO-FT.txt | ||
colo-proxy.txt | ||
conf.py | ||
defs.rst.inc | ||
igd-assign.txt | ||
image-fuzzer.txt | ||
index.rst | ||
memory-hotplug.txt | ||
meson.build | ||
multi-thread-compression.txt | ||
multiseat.txt | ||
nvdimm.txt | ||
pci_expander_bridge.txt | ||
pcie_pci_bridge.txt | ||
pcie_sriov.txt | ||
pcie.txt | ||
pvrdma.txt | ||
qcow2-cache.txt | ||
qdev-device-use.txt | ||
qemu-option-trace.rst.inc | ||
qemupciserial.inf | ||
rdma.txt | ||
spice-port-fqdn.txt | ||
throttle.txt | ||
xbzrle.txt | ||
xen-save-devices-state.txt |