Bin Meng d6150ace2b hw/riscv: microchip_pfsoc: Map EMMC/SD mux register ... Since HSS commit c20a89f8dcac, the Icicle Kit reference design has been updated to use a register mapped at 0x4f000000 instead of a GPIO to control whether eMMC or SD card is to be used. With this support the same HSS image can be used for both eMMC and SD card boot flow, while previously two different board configurations were used. This is undocumented but one can take a look at the HSS code HSS_MMCInit() in services/mmc/mmc_api.c. With this commit, HSS image built from 2020.12 release boots again. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-03-22 21:54:40 -04:00
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boot_opensbi.h	riscv: Add opensbi firmware dynamic support	2020-07-13 17:25:37 -07:00
boot.h	riscv: Pass RISCVHartArrayState by pointer	2021-01-16 14:34:46 -08:00
microchip_pfsoc.h	hw/riscv: microchip_pfsoc: Map EMMC/SD mux register	2021-03-22 21:54:40 -04:00
numa.h	hw/riscv: Add helpers for RISC-V multi-socket NUMA machines	2020-08-25 09:11:35 -07:00
opentitan.h	riscv/opentitan: Update the OpenTitan memory layout	2020-12-17 21:56:44 -08:00
riscv_hart.h	Use OBJECT_DECLARE_SIMPLE_TYPE when possible	2020-09-18 14:12:32 -04:00
sifive_cpu.h	riscv: Add a sifive_cpu.h to include both E and U cpu type defines	2019-09-17 08:42:46 -07:00
sifive_e.h	sifive_e: Rename memmap enum constants	2020-09-18 13:49:48 -04:00
sifive_u.h	hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value	2021-03-04 09:43:29 -05:00
spike.h	riscv: spike: Remove target macro conditionals	2020-12-17 21:56:44 -08:00
virt.h	hw/riscv: Add fw_cfg support to virt	2021-03-22 21:54:40 -04:00