qemu-e2k/target/riscv
Alistair Francis d75377bf7b
RISC-V: Add priv_ver to DisasContext
The gen methods should access state from DisasContext. Add priv_ver
field to the DisasContext struct.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-02-11 15:56:22 -08:00
..
cpu_bits.h
cpu_helper.c RISC-V: Use riscv prefix consistently on cpu helpers 2019-02-11 15:56:21 -08:00
cpu_user.h
cpu.c RISC-V: Implement existential predicates for CSRs 2019-01-09 10:00:56 -08:00
cpu.h RISC-V: Use riscv prefix consistently on cpu helpers 2019-02-11 15:56:21 -08:00
csr.c RISC-V: Use riscv prefix consistently on cpu helpers 2019-02-11 15:56:21 -08:00
fpu_helper.c RISC-V: Use riscv prefix consistently on cpu helpers 2019-02-11 15:56:21 -08:00
gdbstub.c RISC-V: Implement modular CSR helper interface 2019-01-08 13:59:09 -08:00
helper.h
instmap.h
Makefile.objs RISC-V: Implement modular CSR helper interface 2019-01-08 13:59:09 -08:00
op_helper.c RISC-V: Use riscv prefix consistently on cpu helpers 2019-02-11 15:56:21 -08:00
pmp.c target/riscv/pmp.c: Fix pmp_decode_napot() 2018-12-20 12:26:39 -08:00
pmp.h
translate.c RISC-V: Add priv_ver to DisasContext 2019-02-11 15:56:22 -08:00