426 lines
12 KiB
C
426 lines
12 KiB
C
/*
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* Status and system control registers for ARM RealView/Versatile boards.
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL.
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*/
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#include "hw.h"
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#include "qemu/timer.h"
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#include "sysbus.h"
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#include "primecell.h"
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#include "sysemu/sysemu.h"
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#define LOCK_VALUE 0xa05f
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typedef struct {
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SysBusDevice busdev;
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MemoryRegion iomem;
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qemu_irq pl110_mux_ctrl;
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uint32_t sys_id;
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uint32_t leds;
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uint16_t lockval;
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uint32_t cfgdata1;
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uint32_t cfgdata2;
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uint32_t flags;
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uint32_t nvflags;
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uint32_t resetlevel;
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uint32_t proc_id;
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uint32_t sys_mci;
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uint32_t sys_cfgdata;
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uint32_t sys_cfgctrl;
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uint32_t sys_cfgstat;
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uint32_t sys_clcd;
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} arm_sysctl_state;
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static const VMStateDescription vmstate_arm_sysctl = {
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.name = "realview_sysctl",
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.version_id = 3,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(leds, arm_sysctl_state),
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VMSTATE_UINT16(lockval, arm_sysctl_state),
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VMSTATE_UINT32(cfgdata1, arm_sysctl_state),
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VMSTATE_UINT32(cfgdata2, arm_sysctl_state),
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VMSTATE_UINT32(flags, arm_sysctl_state),
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VMSTATE_UINT32(nvflags, arm_sysctl_state),
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VMSTATE_UINT32(resetlevel, arm_sysctl_state),
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VMSTATE_UINT32_V(sys_mci, arm_sysctl_state, 2),
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VMSTATE_UINT32_V(sys_cfgdata, arm_sysctl_state, 2),
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VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2),
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VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2),
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VMSTATE_UINT32_V(sys_clcd, arm_sysctl_state, 3),
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VMSTATE_END_OF_LIST()
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}
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};
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/* The PB926 actually uses a different format for
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* its SYS_ID register. Fortunately the bits which are
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* board type on later boards are distinct.
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*/
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#define BOARD_ID_PB926 0x100
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#define BOARD_ID_EB 0x140
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#define BOARD_ID_PBA8 0x178
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#define BOARD_ID_PBX 0x182
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#define BOARD_ID_VEXPRESS 0x190
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static int board_id(arm_sysctl_state *s)
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{
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/* Extract the board ID field from the SYS_ID register value */
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return (s->sys_id >> 16) & 0xfff;
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}
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static void arm_sysctl_reset(DeviceState *d)
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{
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arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, sysbus_from_qdev(d));
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s->leds = 0;
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s->lockval = 0;
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s->cfgdata1 = 0;
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s->cfgdata2 = 0;
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s->flags = 0;
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s->resetlevel = 0;
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if (board_id(s) == BOARD_ID_VEXPRESS) {
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/* On VExpress this register will RAZ/WI */
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s->sys_clcd = 0;
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} else {
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/* All others: CLCDID 0x1f, indicating VGA */
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s->sys_clcd = 0x1f00;
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}
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}
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static uint64_t arm_sysctl_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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arm_sysctl_state *s = (arm_sysctl_state *)opaque;
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switch (offset) {
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case 0x00: /* ID */
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return s->sys_id;
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case 0x04: /* SW */
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/* General purpose hardware switches.
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We don't have a useful way of exposing these to the user. */
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return 0;
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case 0x08: /* LED */
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return s->leds;
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case 0x20: /* LOCK */
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return s->lockval;
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case 0x0c: /* OSC0 */
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case 0x10: /* OSC1 */
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case 0x14: /* OSC2 */
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case 0x18: /* OSC3 */
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case 0x1c: /* OSC4 */
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case 0x24: /* 100HZ */
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/* ??? Implement these. */
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return 0;
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case 0x28: /* CFGDATA1 */
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return s->cfgdata1;
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case 0x2c: /* CFGDATA2 */
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return s->cfgdata2;
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case 0x30: /* FLAGS */
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return s->flags;
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case 0x38: /* NVFLAGS */
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return s->nvflags;
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case 0x40: /* RESETCTL */
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if (board_id(s) == BOARD_ID_VEXPRESS) {
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/* reserved: RAZ/WI */
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return 0;
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}
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return s->resetlevel;
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case 0x44: /* PCICTL */
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return 1;
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case 0x48: /* MCI */
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return s->sys_mci;
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case 0x4c: /* FLASH */
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return 0;
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case 0x50: /* CLCD */
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return s->sys_clcd;
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case 0x54: /* CLCDSER */
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return 0;
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case 0x58: /* BOOTCS */
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return 0;
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case 0x5c: /* 24MHz */
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return muldiv64(qemu_get_clock_ns(vm_clock), 24000000, get_ticks_per_sec());
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case 0x60: /* MISC */
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return 0;
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case 0x84: /* PROCID0 */
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return s->proc_id;
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case 0x88: /* PROCID1 */
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return 0xff000000;
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case 0x64: /* DMAPSR0 */
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case 0x68: /* DMAPSR1 */
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case 0x6c: /* DMAPSR2 */
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case 0x70: /* IOSEL */
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case 0x74: /* PLDCTL */
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case 0x80: /* BUSID */
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case 0x8c: /* OSCRESET0 */
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case 0x90: /* OSCRESET1 */
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case 0x94: /* OSCRESET2 */
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case 0x98: /* OSCRESET3 */
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case 0x9c: /* OSCRESET4 */
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case 0xc0: /* SYS_TEST_OSC0 */
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case 0xc4: /* SYS_TEST_OSC1 */
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case 0xc8: /* SYS_TEST_OSC2 */
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case 0xcc: /* SYS_TEST_OSC3 */
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case 0xd0: /* SYS_TEST_OSC4 */
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return 0;
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case 0xa0: /* SYS_CFGDATA */
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if (board_id(s) != BOARD_ID_VEXPRESS) {
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goto bad_reg;
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}
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return s->sys_cfgdata;
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case 0xa4: /* SYS_CFGCTRL */
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if (board_id(s) != BOARD_ID_VEXPRESS) {
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goto bad_reg;
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}
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return s->sys_cfgctrl;
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case 0xa8: /* SYS_CFGSTAT */
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if (board_id(s) != BOARD_ID_VEXPRESS) {
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goto bad_reg;
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}
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return s->sys_cfgstat;
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default:
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bad_reg:
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qemu_log_mask(LOG_GUEST_ERROR,
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"arm_sysctl_read: Bad register offset 0x%x\n",
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(int)offset);
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return 0;
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}
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}
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static void arm_sysctl_write(void *opaque, hwaddr offset,
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uint64_t val, unsigned size)
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{
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arm_sysctl_state *s = (arm_sysctl_state *)opaque;
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switch (offset) {
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case 0x08: /* LED */
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s->leds = val;
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case 0x0c: /* OSC0 */
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case 0x10: /* OSC1 */
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case 0x14: /* OSC2 */
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case 0x18: /* OSC3 */
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case 0x1c: /* OSC4 */
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/* ??? */
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break;
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case 0x20: /* LOCK */
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if (val == LOCK_VALUE)
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s->lockval = val;
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else
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s->lockval = val & 0x7fff;
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break;
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case 0x28: /* CFGDATA1 */
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/* ??? Need to implement this. */
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s->cfgdata1 = val;
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break;
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case 0x2c: /* CFGDATA2 */
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/* ??? Need to implement this. */
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s->cfgdata2 = val;
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break;
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case 0x30: /* FLAGSSET */
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s->flags |= val;
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break;
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case 0x34: /* FLAGSCLR */
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s->flags &= ~val;
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break;
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case 0x38: /* NVFLAGSSET */
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s->nvflags |= val;
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break;
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case 0x3c: /* NVFLAGSCLR */
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s->nvflags &= ~val;
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break;
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case 0x40: /* RESETCTL */
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switch (board_id(s)) {
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case BOARD_ID_PB926:
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if (s->lockval == LOCK_VALUE) {
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s->resetlevel = val;
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if (val & 0x100) {
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qemu_system_reset_request();
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}
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}
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break;
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case BOARD_ID_PBX:
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case BOARD_ID_PBA8:
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if (s->lockval == LOCK_VALUE) {
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s->resetlevel = val;
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if (val & 0x04) {
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qemu_system_reset_request();
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}
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}
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break;
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case BOARD_ID_VEXPRESS:
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case BOARD_ID_EB:
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default:
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/* reserved: RAZ/WI */
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break;
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}
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break;
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case 0x44: /* PCICTL */
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/* nothing to do. */
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break;
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case 0x4c: /* FLASH */
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break;
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case 0x50: /* CLCD */
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switch (board_id(s)) {
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case BOARD_ID_PB926:
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/* On 926 bits 13:8 are R/O, bits 1:0 control
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* the mux that defines how to interpret the PL110
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* graphics format, and other bits are r/w but we
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* don't implement them to do anything.
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*/
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s->sys_clcd &= 0x3f00;
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s->sys_clcd |= val & ~0x3f00;
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qemu_set_irq(s->pl110_mux_ctrl, val & 3);
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break;
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case BOARD_ID_EB:
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/* The EB is the same except that there is no mux since
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* the EB has a PL111.
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*/
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s->sys_clcd &= 0x3f00;
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s->sys_clcd |= val & ~0x3f00;
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break;
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case BOARD_ID_PBA8:
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case BOARD_ID_PBX:
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/* On PBA8 and PBX bit 7 is r/w and all other bits
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* are either r/o or RAZ/WI.
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*/
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s->sys_clcd &= (1 << 7);
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s->sys_clcd |= val & ~(1 << 7);
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break;
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case BOARD_ID_VEXPRESS:
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default:
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/* On VExpress this register is unimplemented and will RAZ/WI */
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break;
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}
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case 0x54: /* CLCDSER */
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case 0x64: /* DMAPSR0 */
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case 0x68: /* DMAPSR1 */
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case 0x6c: /* DMAPSR2 */
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case 0x70: /* IOSEL */
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case 0x74: /* PLDCTL */
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case 0x80: /* BUSID */
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case 0x84: /* PROCID0 */
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case 0x88: /* PROCID1 */
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case 0x8c: /* OSCRESET0 */
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case 0x90: /* OSCRESET1 */
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case 0x94: /* OSCRESET2 */
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case 0x98: /* OSCRESET3 */
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case 0x9c: /* OSCRESET4 */
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break;
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case 0xa0: /* SYS_CFGDATA */
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if (board_id(s) != BOARD_ID_VEXPRESS) {
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goto bad_reg;
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}
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s->sys_cfgdata = val;
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return;
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case 0xa4: /* SYS_CFGCTRL */
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if (board_id(s) != BOARD_ID_VEXPRESS) {
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goto bad_reg;
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}
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s->sys_cfgctrl = val & ~(3 << 18);
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s->sys_cfgstat = 1; /* complete */
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switch (s->sys_cfgctrl) {
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case 0xc0800000: /* SYS_CFG_SHUTDOWN to motherboard */
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qemu_system_shutdown_request();
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break;
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case 0xc0900000: /* SYS_CFG_REBOOT to motherboard */
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qemu_system_reset_request();
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break;
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default:
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s->sys_cfgstat |= 2; /* error */
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}
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return;
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case 0xa8: /* SYS_CFGSTAT */
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if (board_id(s) != BOARD_ID_VEXPRESS) {
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goto bad_reg;
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}
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s->sys_cfgstat = val & 3;
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return;
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default:
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bad_reg:
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qemu_log_mask(LOG_GUEST_ERROR,
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"arm_sysctl_write: Bad register offset 0x%x\n",
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(int)offset);
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return;
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}
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}
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static const MemoryRegionOps arm_sysctl_ops = {
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.read = arm_sysctl_read,
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.write = arm_sysctl_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void arm_sysctl_gpio_set(void *opaque, int line, int level)
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{
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arm_sysctl_state *s = (arm_sysctl_state *)opaque;
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switch (line) {
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case ARM_SYSCTL_GPIO_MMC_WPROT:
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{
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/* For PB926 and EB write-protect is bit 2 of SYS_MCI;
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* for all later boards it is bit 1.
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*/
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int bit = 2;
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if ((board_id(s) == BOARD_ID_PB926) || (board_id(s) == BOARD_ID_EB)) {
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bit = 4;
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}
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s->sys_mci &= ~bit;
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if (level) {
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s->sys_mci |= bit;
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}
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break;
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}
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case ARM_SYSCTL_GPIO_MMC_CARDIN:
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s->sys_mci &= ~1;
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if (level) {
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s->sys_mci |= 1;
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}
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break;
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}
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}
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static int arm_sysctl_init(SysBusDevice *dev)
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{
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arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
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memory_region_init_io(&s->iomem, &arm_sysctl_ops, s, "arm-sysctl", 0x1000);
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sysbus_init_mmio(dev, &s->iomem);
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qdev_init_gpio_in(&s->busdev.qdev, arm_sysctl_gpio_set, 2);
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qdev_init_gpio_out(&s->busdev.qdev, &s->pl110_mux_ctrl, 1);
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return 0;
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}
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static Property arm_sysctl_properties[] = {
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DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0),
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DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void arm_sysctl_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = arm_sysctl_init;
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dc->reset = arm_sysctl_reset;
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dc->vmsd = &vmstate_arm_sysctl;
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dc->props = arm_sysctl_properties;
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}
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static TypeInfo arm_sysctl_info = {
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.name = "realview_sysctl",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(arm_sysctl_state),
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.class_init = arm_sysctl_class_init,
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};
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static void arm_sysctl_register_types(void)
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{
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type_register_static(&arm_sysctl_info);
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}
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type_init(arm_sysctl_register_types)
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