Alexander Wagner d11e316d84 hw/riscv: Fix OT IBEX reset vector ... The IBEX documentation [1] specifies the reset vector to be "the most significant 3 bytes of the boot address and the reset value (0x80) as the least significant byte". [1] https://github.com/lowRISC/ibex/blob/master/doc/03_reference/exception_interrupts.rst Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210420080008.119798-1-alexander.wagner@ulal.de Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-05-11 20:02:07 +10:00
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boot.c
Kconfig	hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine	2021-05-11 20:02:06 +10:00
meson.build
microchip_pfsoc.c
numa.c
opentitan.c	hw/riscv: Fix OT IBEX reset vector	2021-05-11 20:02:07 +10:00
riscv_hart.c
shakti_c.c	hw/riscv: Connect Shakti UART to Shakti platform	2021-05-11 20:02:06 +10:00
sifive_e.c
sifive_u.c
spike.c
virt.c