qemu-e2k/target-arm
Andrew Jones d8e052b387 target-arm: get_phys_addr_lpae: more xn control
This patch makes the following changes to the determination of
whether an address is executable, when translating addresses
using LPAE.

1. No longer assumes that PL0 can't execute when it can't read.
   It can in AArch64, a difference from AArch32.
2. Use va_size == 64 to determine we're in AArch64, rather than
   arm_feature(env, ARM_FEATURE_V8), which is insufficient.
3. Add additional XN determinants
   - NS && is_secure && (SCR & SCR_SIF)
   - WXN && (prot & PAGE_WRITE)
   - AArch64: (prot_PL0 & PAGE_WRITE)
   - AArch32: UWXN && (prot_PL0 & PAGE_WRITE)
   - XN determination should also work in secure mode (untested)
   - XN may even work in EL2 (currently impossible to test)
4. Cleans up the bloated PAGE_EXEC condition - by removing it.

The helper get_S1prot is introduced. It may even work in EL2,
when support for that comes, but, as the function name implies,
it only works for stage 1 translations.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Message-id: 1426099139-14463-4-git-send-email-drjones@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-03-16 12:30:46 +00:00
..
arm_ldst.h softmmu: introduce cpu_ldst.h 2014-06-05 16:10:33 +02:00
arm-semi.c Pass semihosting exit code back to system. 2014-12-11 12:07:48 +00:00
cpu64.c target-arm: Add missing compatible property to A57 2015-03-11 13:21:06 +00:00
cpu-qom.h target-arm: Add ARMCPU secure property 2014-12-22 23:12:28 +00:00
cpu.c target-arm: Add CPU property to disable AArch64 2015-02-13 05:46:08 +00:00
cpu.h cpu: Make cpu_init() return QOM CPUState object 2015-03-10 17:33:51 +01:00
crypto_helper.c target-arm: crypto: fix BE host support 2015-01-16 11:54:29 +00:00
gdbstub64.c target-arm/gdbstub64.c: remove useless 'break' statement. 2014-04-17 21:34:06 +01:00
gdbstub.c cpu: Introduce CPUClass::gdb_{read,write}_register() 2013-07-27 00:04:17 +02:00
helper-a64.c target-arm: Add 32/64-bit register sync 2015-02-13 05:46:08 +00:00
helper-a64.h target-arm: A64: Implement CRC instructions 2014-06-09 16:06:12 +01:00
helper.c target-arm: get_phys_addr_lpae: more xn control 2015-03-16 12:30:46 +00:00
helper.h target-arm: A64: Emulate the SMC insn 2014-09-29 18:48:50 +01:00
internals.h target-arm: make TTBCR banked 2014-12-11 12:07:51 +00:00
iwmmxt_helper.c target-arm: Delete unused iwmmxt_msadb helper 2014-06-09 16:06:12 +01:00
kvm32.c target-arm/kvm: make reg sync code common between kvm32/64 2014-12-11 12:07:53 +00:00
kvm64.c target-arm: Add AArch32 guest support to KVM64 2015-02-13 05:46:08 +00:00
kvm_arm.h target-arm/kvm: make reg sync code common between kvm32/64 2014-12-11 12:07:53 +00:00
kvm-consts.h target-arm: add missing PSCI constants needed for PSCI emulation 2014-10-24 12:19:12 +01:00
kvm-stub.c target-arm: Initialize cpreg list from KVM when using KVM 2013-06-25 18:16:10 +01:00
kvm.c kvm: add machine state to kvm_arch_init 2015-03-11 18:16:17 +01:00
machine.c vmstate: accept QEMUTimer in VMSTATE_TIMER*, add VMSTATE_TIMER_PTR* 2015-01-26 12:22:44 +01:00
Makefile.objs target-arm: add emulation of PSCI calls for system emulation 2014-10-24 12:19:13 +01:00
neon_helper.c target-arm: add support for v8 VMULL.P64 instruction 2014-06-09 16:06:11 +01:00
op_addsub.h
op_helper.c target-arm: Add 32/64-bit register sync 2015-02-13 05:46:08 +00:00
psci.c target-arm: add emulation of PSCI calls for system emulation 2014-10-24 12:19:13 +01:00
translate-a64.c tcg: Change translator-side labels to a pointer 2015-03-13 12:28:18 -07:00
translate.c tcg: Change translator-side labels to a pointer 2015-03-13 12:28:18 -07:00
translate.h tcg: Change translator-side labels to a pointer 2015-03-13 12:28:18 -07:00