110 lines
3.6 KiB
C
110 lines
3.6 KiB
C
/*
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* ARM AdvSIMD / SVE Vector Operations
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*
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* Copyright (c) 2018 Linaro
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "tcg/tcg-gvec-desc.h"
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#define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q
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/* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */
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static uint16_t inl_qrdmlah_s16(CPUARMState *env, int16_t src1,
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int16_t src2, int16_t src3)
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{
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/* Simplify:
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* = ((a3 << 16) + ((e1 * e2) << 1) + (1 << 15)) >> 16
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* = ((a3 << 15) + (e1 * e2) + (1 << 14)) >> 15
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*/
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int32_t ret = (int32_t)src1 * src2;
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ret = ((int32_t)src3 << 15) + ret + (1 << 14);
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ret >>= 15;
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if (ret != (int16_t)ret) {
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SET_QC();
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ret = (ret < 0 ? -0x8000 : 0x7fff);
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}
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return ret;
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}
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uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1,
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uint32_t src2, uint32_t src3)
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{
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uint16_t e1 = inl_qrdmlah_s16(env, src1, src2, src3);
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uint16_t e2 = inl_qrdmlah_s16(env, src1 >> 16, src2 >> 16, src3 >> 16);
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return deposit32(e1, 16, 16, e2);
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}
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/* Signed saturating rounding doubling multiply-subtract high half, 16-bit */
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static uint16_t inl_qrdmlsh_s16(CPUARMState *env, int16_t src1,
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int16_t src2, int16_t src3)
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{
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/* Similarly, using subtraction:
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* = ((a3 << 16) - ((e1 * e2) << 1) + (1 << 15)) >> 16
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* = ((a3 << 15) - (e1 * e2) + (1 << 14)) >> 15
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*/
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int32_t ret = (int32_t)src1 * src2;
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ret = ((int32_t)src3 << 15) - ret + (1 << 14);
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ret >>= 15;
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if (ret != (int16_t)ret) {
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SET_QC();
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ret = (ret < 0 ? -0x8000 : 0x7fff);
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}
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return ret;
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}
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uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1,
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uint32_t src2, uint32_t src3)
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{
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uint16_t e1 = inl_qrdmlsh_s16(env, src1, src2, src3);
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uint16_t e2 = inl_qrdmlsh_s16(env, src1 >> 16, src2 >> 16, src3 >> 16);
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return deposit32(e1, 16, 16, e2);
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}
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/* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */
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uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1,
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int32_t src2, int32_t src3)
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{
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/* Simplify similarly to int_qrdmlah_s16 above. */
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int64_t ret = (int64_t)src1 * src2;
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ret = ((int64_t)src3 << 31) + ret + (1 << 30);
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ret >>= 31;
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if (ret != (int32_t)ret) {
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SET_QC();
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ret = (ret < 0 ? INT32_MIN : INT32_MAX);
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}
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return ret;
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}
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/* Signed saturating rounding doubling multiply-subtract high half, 32-bit */
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uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1,
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int32_t src2, int32_t src3)
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{
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/* Simplify similarly to int_qrdmlsh_s16 above. */
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int64_t ret = (int64_t)src1 * src2;
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ret = ((int64_t)src3 << 31) - ret + (1 << 30);
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ret >>= 31;
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if (ret != (int32_t)ret) {
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SET_QC();
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ret = (ret < 0 ? INT32_MIN : INT32_MAX);
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}
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return ret;
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}
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