211 lines
5.6 KiB
C
211 lines
5.6 KiB
C
/*
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* Heathrow PIC support (OldWorld PowerMac)
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*
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* Copyright (c) 2005-2007 Fabrice Bellard
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/ppc/mac.h"
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#include "migration/vmstate.h"
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#include "qemu/module.h"
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#include "hw/intc/heathrow_pic.h"
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#include "hw/irq.h"
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#include "trace.h"
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static inline int heathrow_check_irq(HeathrowPICState *pic)
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{
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return (pic->events | (pic->levels & pic->level_triggered)) & pic->mask;
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}
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/* update the CPU irq state */
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static void heathrow_update_irq(HeathrowState *s)
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{
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if (heathrow_check_irq(&s->pics[0]) ||
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heathrow_check_irq(&s->pics[1])) {
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qemu_irq_raise(s->irqs[0]);
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} else {
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qemu_irq_lower(s->irqs[0]);
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}
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}
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static void heathrow_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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HeathrowState *s = opaque;
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HeathrowPICState *pic;
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unsigned int n;
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n = ((addr & 0xfff) - 0x10) >> 4;
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trace_heathrow_write(addr, n, value);
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if (n >= 2)
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return;
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pic = &s->pics[n];
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switch(addr & 0xf) {
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case 0x04:
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pic->mask = value;
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heathrow_update_irq(s);
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break;
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case 0x08:
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/* do not reset level triggered IRQs */
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value &= ~pic->level_triggered;
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pic->events &= ~value;
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heathrow_update_irq(s);
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break;
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default:
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break;
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}
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}
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static uint64_t heathrow_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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HeathrowState *s = opaque;
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HeathrowPICState *pic;
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unsigned int n;
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uint32_t value;
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n = ((addr & 0xfff) - 0x10) >> 4;
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if (n >= 2) {
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value = 0;
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} else {
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pic = &s->pics[n];
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switch(addr & 0xf) {
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case 0x0:
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value = pic->events;
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break;
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case 0x4:
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value = pic->mask;
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break;
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case 0xc:
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value = pic->levels;
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break;
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default:
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value = 0;
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break;
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}
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}
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trace_heathrow_read(addr, n, value);
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return value;
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}
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static const MemoryRegionOps heathrow_ops = {
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.read = heathrow_read,
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.write = heathrow_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void heathrow_set_irq(void *opaque, int num, int level)
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{
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HeathrowState *s = opaque;
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HeathrowPICState *pic;
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unsigned int irq_bit;
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int last_level;
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pic = &s->pics[1 - (num >> 5)];
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irq_bit = 1 << (num & 0x1f);
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last_level = (pic->levels & irq_bit) ? 1 : 0;
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if (level) {
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pic->events |= irq_bit & ~pic->level_triggered;
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pic->levels |= irq_bit;
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} else {
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pic->levels &= ~irq_bit;
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}
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if (last_level != level) {
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trace_heathrow_set_irq(num, level);
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}
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heathrow_update_irq(s);
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}
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static const VMStateDescription vmstate_heathrow_pic_one = {
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.name = "heathrow_pic_one",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(events, HeathrowPICState),
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VMSTATE_UINT32(mask, HeathrowPICState),
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VMSTATE_UINT32(levels, HeathrowPICState),
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VMSTATE_UINT32(level_triggered, HeathrowPICState),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_heathrow = {
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.name = "heathrow_pic",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_STRUCT_ARRAY(pics, HeathrowState, 2, 1,
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vmstate_heathrow_pic_one, HeathrowPICState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void heathrow_reset(DeviceState *d)
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{
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HeathrowState *s = HEATHROW(d);
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s->pics[0].level_triggered = 0;
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s->pics[1].level_triggered = 0x1ff00000;
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}
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static void heathrow_init(Object *obj)
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{
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HeathrowState *s = HEATHROW(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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/* only 1 CPU */
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qdev_init_gpio_out(DEVICE(obj), s->irqs, 1);
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qdev_init_gpio_in(DEVICE(obj), heathrow_set_irq, HEATHROW_NUM_IRQS);
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memory_region_init_io(&s->mem, OBJECT(s), &heathrow_ops, s,
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"heathrow-pic", 0x1000);
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sysbus_init_mmio(sbd, &s->mem);
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}
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static void heathrow_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->reset = heathrow_reset;
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dc->vmsd = &vmstate_heathrow;
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set_bit(DEVICE_CATEGORY_MISC, dc->categories);
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}
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static const TypeInfo heathrow_type_info = {
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.name = TYPE_HEATHROW,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(HeathrowState),
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.instance_init = heathrow_init,
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.class_init = heathrow_class_init,
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};
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static void heathrow_register_types(void)
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{
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type_register_static(&heathrow_type_info);
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}
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type_init(heathrow_register_types)
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