Peter Maydell da5141fc45 target-arm: VFPv4 implies half-precision extension ... VFPv4 implies the presence of the half-precision floating point extension (which is optional in VFPv3). Add this implied rule to arm_cpu_realizefn() and remove some no-longer-needed explicit setting of the bit in initfns. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-5-git-send-email-peter.maydell@linaro.org		2014-06-09 16:06:11 +01:00
..
arm_ldst.h
arm-semi.c
cpu64.c	target-arm: VFPv4 implies half-precision extension	2014-06-09 16:06:11 +01:00
cpu-qom.h
cpu.c	target-arm: VFPv4 implies half-precision extension	2014-06-09 16:06:11 +01:00
cpu.h	target-arm: add support for v8 VMULL.P64 instruction	2014-06-09 16:06:11 +01:00
crypto_helper.c
gdbstub64.c
gdbstub.c
helper-a64.c	target-arm: add support for v8 VMULL.P64 instruction	2014-06-09 16:06:11 +01:00
helper-a64.h	target-arm: add support for v8 VMULL.P64 instruction	2014-06-09 16:06:11 +01:00
helper.c
helper.h	target-arm: add support for v8 VMULL.P64 instruction	2014-06-09 16:06:11 +01:00
internals.h
iwmmxt_helper.c
kvm32.c
kvm64.c
kvm_arm.h
kvm-consts.h
kvm-stub.c
kvm.c
machine.c
Makefile.objs
neon_helper.c	target-arm: add support for v8 VMULL.P64 instruction	2014-06-09 16:06:11 +01:00
op_addsub.h
op_helper.c
translate-a64.c	target-arm: A64: Use PMULL feature bit for PMULL	2014-06-09 16:06:11 +01:00
translate.c	target-arm: add support for v8 VMULL.P64 instruction	2014-06-09 16:06:11 +01:00
translate.h