dfa3c4c57e
Add a new profile CPU 'rva22s64' to work as an alias of -cpu rv64i,rva22s64 Like the existing rva22u64 CPU already does with the RVA22U64 profile. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20231218125334.37184-27-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
54 lines
2.4 KiB
C
54 lines
2.4 KiB
C
/*
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* QEMU RISC-V CPU QOM header (target agnostic)
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*
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* Copyright (c) 2023 Ventana Micro Systems Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef RISCV_CPU_QOM_H
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#define RISCV_CPU_QOM_H
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#include "hw/core/cpu.h"
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#define TYPE_RISCV_CPU "riscv-cpu"
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#define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu"
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#define TYPE_RISCV_VENDOR_CPU "riscv-vendor-cpu"
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#define TYPE_RISCV_BARE_CPU "riscv-bare-cpu"
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#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
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#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
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#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
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#define TYPE_RISCV_CPU_MAX RISCV_CPU_TYPE_NAME("max")
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#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
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#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
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#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
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#define TYPE_RISCV_CPU_RV64I RISCV_CPU_TYPE_NAME("rv64i")
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#define TYPE_RISCV_CPU_RVA22U64 RISCV_CPU_TYPE_NAME("rva22u64")
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#define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64")
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#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
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#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
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#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
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#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
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#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
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#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
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#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
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#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906")
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#define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1")
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#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
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OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
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#endif /* RISCV_CPU_QOM_H */
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