331 lines
11 KiB
C
331 lines
11 KiB
C
/*
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* QEMU MCH/ICH9 PCI Bridge Emulation
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*
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* Copyright (c) 2006 Fabrice Bellard
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* Copyright (c) 2009, 2010, 2011
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* Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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* Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
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*
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* This is based on piix_pci.c, but heavily modified.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/hw.h"
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#include "hw/pci-host/q35.h"
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/****************************************************************************
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* Q35 host
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*/
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static void q35_host_realize(DeviceState *dev, Error **errp)
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{
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PCIHostState *pci = PCI_HOST_BRIDGE(dev);
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Q35PCIHost *s = Q35_HOST_DEVICE(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem);
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sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4);
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sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem);
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sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4);
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if (pcie_host_init(PCIE_HOST_BRIDGE(s)) < 0) {
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error_setg(errp, "failed to initialize pcie host");
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return;
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}
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pci->bus = pci_bus_new(DEVICE(s), "pcie.0",
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s->mch.pci_address_space, s->mch.address_space_io,
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0, TYPE_PCIE_BUS);
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qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus));
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qdev_init_nofail(DEVICE(&s->mch));
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}
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static const char *q35_host_root_bus_path(PCIHostState *host_bridge,
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PCIBus *rootbus)
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{
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/* For backwards compat with old device paths */
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return "0000";
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}
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static Property mch_props[] = {
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DEFINE_PROP_UINT64("MCFG", Q35PCIHost, parent_obj.base_addr,
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MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void q35_host_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
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hc->root_bus_path = q35_host_root_bus_path;
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dc->realize = q35_host_realize;
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dc->props = mch_props;
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dc->fw_name = "pci";
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}
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static void q35_host_initfn(Object *obj)
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{
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Q35PCIHost *s = Q35_HOST_DEVICE(obj);
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PCIHostState *phb = PCI_HOST_BRIDGE(obj);
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memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb,
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"pci-conf-idx", 4);
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memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb,
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"pci-conf-data", 4);
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object_initialize(&s->mch, TYPE_MCH_PCI_DEVICE);
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object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL);
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qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0));
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qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false);
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}
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static const TypeInfo q35_host_info = {
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.name = TYPE_Q35_HOST_DEVICE,
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.parent = TYPE_PCIE_HOST_BRIDGE,
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.instance_size = sizeof(Q35PCIHost),
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.instance_init = q35_host_initfn,
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.class_init = q35_host_class_init,
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};
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/****************************************************************************
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* MCH D0:F0
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*/
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/* PCIe MMCFG */
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static void mch_update_pciexbar(MCHPCIState *mch)
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{
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PCIDevice *pci_dev = PCI_DEVICE(mch);
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BusState *bus = qdev_get_parent_bus(DEVICE(mch));
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PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent);
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uint64_t pciexbar;
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int enable;
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uint64_t addr;
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uint64_t addr_mask;
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uint32_t length;
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pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR);
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enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN;
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addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK;
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switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) {
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case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M:
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length = 256 * 1024 * 1024;
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break;
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case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M:
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length = 128 * 1024 * 1024;
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addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK |
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MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
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break;
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case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M:
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length = 64 * 1024 * 1024;
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addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
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break;
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case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD:
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default:
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enable = 0;
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length = 0;
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abort();
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break;
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}
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addr = pciexbar & addr_mask;
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pcie_host_mmcfg_update(pehb, enable, addr, length);
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}
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/* PAM */
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static void mch_update_pam(MCHPCIState *mch)
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{
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PCIDevice *pd = PCI_DEVICE(mch);
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int i;
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memory_region_transaction_begin();
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for (i = 0; i < 13; i++) {
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pam_update(&mch->pam_regions[i], i,
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pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]);
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}
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memory_region_transaction_commit();
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}
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/* SMRAM */
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static void mch_update_smram(MCHPCIState *mch)
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{
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PCIDevice *pd = PCI_DEVICE(mch);
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memory_region_transaction_begin();
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smram_update(&mch->smram_region, pd->config[MCH_HOST_BRDIGE_SMRAM],
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mch->smm_enabled);
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memory_region_transaction_commit();
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}
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static void mch_set_smm(int smm, void *arg)
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{
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MCHPCIState *mch = arg;
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PCIDevice *pd = PCI_DEVICE(mch);
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memory_region_transaction_begin();
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smram_set_smm(&mch->smm_enabled, smm, pd->config[MCH_HOST_BRDIGE_SMRAM],
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&mch->smram_region);
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memory_region_transaction_commit();
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}
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static void mch_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len)
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{
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MCHPCIState *mch = MCH_PCI_DEVICE(d);
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/* XXX: implement SMRAM.D_LOCK */
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pci_default_write_config(d, address, val, len);
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if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0,
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MCH_HOST_BRIDGE_PAM_SIZE)) {
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mch_update_pam(mch);
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}
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if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR,
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MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) {
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mch_update_pciexbar(mch);
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}
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if (ranges_overlap(address, len, MCH_HOST_BRDIGE_SMRAM,
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MCH_HOST_BRDIGE_SMRAM_SIZE)) {
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mch_update_smram(mch);
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}
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}
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static void mch_update(MCHPCIState *mch)
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{
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mch_update_pciexbar(mch);
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mch_update_pam(mch);
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mch_update_smram(mch);
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}
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static int mch_post_load(void *opaque, int version_id)
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{
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MCHPCIState *mch = opaque;
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mch_update(mch);
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return 0;
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}
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static const VMStateDescription vmstate_mch = {
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.name = "mch",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.post_load = mch_post_load,
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.fields = (VMStateField []) {
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VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState),
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VMSTATE_UINT8(smm_enabled, MCHPCIState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void mch_reset(DeviceState *qdev)
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{
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PCIDevice *d = PCI_DEVICE(qdev);
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MCHPCIState *mch = MCH_PCI_DEVICE(d);
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pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR,
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MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
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d->config[MCH_HOST_BRDIGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
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mch_update(mch);
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}
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static int mch_init(PCIDevice *d)
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{
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int i;
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hwaddr pci_hole64_size;
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MCHPCIState *mch = MCH_PCI_DEVICE(d);
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/* Leave enough space for the biggest MCFG BAR */
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/* TODO: this matches current bios behaviour, but
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* it's not a power of two, which means an MTRR
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* can't cover it exactly.
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*/
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mch->guest_info->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT +
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MCH_HOST_BRIDGE_PCIEXBAR_MAX;
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/* setup pci memory regions */
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memory_region_init_alias(&mch->pci_hole, OBJECT(mch), "pci-hole",
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mch->pci_address_space,
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mch->below_4g_mem_size,
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0x100000000ULL - mch->below_4g_mem_size);
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memory_region_add_subregion(mch->system_memory, mch->below_4g_mem_size,
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&mch->pci_hole);
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pci_hole64_size = (sizeof(hwaddr) == 4 ? 0 :
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((uint64_t)1 << 62));
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memory_region_init_alias(&mch->pci_hole_64bit, OBJECT(mch), "pci-hole64",
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mch->pci_address_space,
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0x100000000ULL + mch->above_4g_mem_size,
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pci_hole64_size);
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if (pci_hole64_size) {
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memory_region_add_subregion(mch->system_memory,
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0x100000000ULL + mch->above_4g_mem_size,
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&mch->pci_hole_64bit);
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}
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/* smram */
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cpu_smm_register(&mch_set_smm, mch);
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memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region",
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mch->pci_address_space, 0xa0000, 0x20000);
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memory_region_add_subregion_overlap(mch->system_memory, 0xa0000,
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&mch->smram_region, 1);
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memory_region_set_enabled(&mch->smram_region, false);
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init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, mch->pci_address_space,
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&mch->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
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for (i = 0; i < 12; ++i) {
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init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, mch->pci_address_space,
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&mch->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
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PAM_EXPAN_SIZE);
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}
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return 0;
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}
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static void mch_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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k->init = mch_init;
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k->config_write = mch_write_config;
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dc->reset = mch_reset;
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dc->desc = "Host bridge";
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dc->vmsd = &vmstate_mch;
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k->vendor_id = PCI_VENDOR_ID_INTEL;
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k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH;
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k->revision = MCH_HOST_BRIDGE_REVISION_DEFUALT;
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k->class_id = PCI_CLASS_BRIDGE_HOST;
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}
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static const TypeInfo mch_info = {
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.name = TYPE_MCH_PCI_DEVICE,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(MCHPCIState),
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.class_init = mch_class_init,
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};
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static void q35_register(void)
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{
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type_register_static(&mch_info);
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type_register_static(&q35_host_info);
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}
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type_init(q35_register);
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