18df0b4695
We extend RISC-V virt machine to allow creating a multi-socket machine. Each RISC-V virt machine socket is a NUMA node having a set of HARTs, a memory instance, a CLINT instance, and a PLIC instance. Other devices are shared between all sockets. We also update the generated device tree accordingly. By default, NUMA multi-socket support is disabled for RISC-V virt machine. To enable it, users can use "-numa" command-line options of QEMU. Example1: For two NUMA nodes with 2 CPUs each, append following to command-line options: "-smp 4 -numa node -numa node" Example2: For two NUMA nodes with 1 and 3 CPUs, append following to command-line options: "-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \ -numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \ -numa cpu,node-id=1,core-id=3" The maximum number of sockets in a RISC-V virt machine is 8 but this limit can be changed in future. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Message-Id: <20200616032229.766089-6-anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
97 lines
2.5 KiB
C
97 lines
2.5 KiB
C
/*
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* QEMU RISC-V VirtIO machine interface
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*
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* Copyright (c) 2017 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_RISCV_VIRT_H
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#define HW_RISCV_VIRT_H
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#include "hw/riscv/riscv_hart.h"
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#include "hw/sysbus.h"
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#include "hw/block/flash.h"
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#define VIRT_CPUS_MAX 8
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#define VIRT_SOCKETS_MAX 8
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#define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
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#define RISCV_VIRT_MACHINE(obj) \
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OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_MACHINE)
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typedef struct {
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/*< private >*/
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MachineState parent;
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/*< public >*/
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RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
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DeviceState *plic[VIRT_SOCKETS_MAX];
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PFlashCFI01 *flash[2];
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void *fdt;
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int fdt_size;
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} RISCVVirtState;
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enum {
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VIRT_DEBUG,
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VIRT_MROM,
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VIRT_TEST,
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VIRT_RTC,
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VIRT_CLINT,
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VIRT_PLIC,
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VIRT_UART0,
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VIRT_VIRTIO,
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VIRT_FLASH,
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VIRT_DRAM,
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VIRT_PCIE_MMIO,
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VIRT_PCIE_PIO,
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VIRT_PCIE_ECAM
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};
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enum {
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UART0_IRQ = 10,
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RTC_IRQ = 11,
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VIRTIO_IRQ = 1, /* 1 to 8 */
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VIRTIO_COUNT = 8,
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PCIE_IRQ = 0x20, /* 32 to 35 */
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VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
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};
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#define VIRT_PLIC_HART_CONFIG "MS"
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#define VIRT_PLIC_NUM_SOURCES 127
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#define VIRT_PLIC_NUM_PRIORITIES 7
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#define VIRT_PLIC_PRIORITY_BASE 0x04
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#define VIRT_PLIC_PENDING_BASE 0x1000
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#define VIRT_PLIC_ENABLE_BASE 0x2000
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#define VIRT_PLIC_ENABLE_STRIDE 0x80
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#define VIRT_PLIC_CONTEXT_BASE 0x200000
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#define VIRT_PLIC_CONTEXT_STRIDE 0x1000
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#define VIRT_PLIC_SIZE(__num_context) \
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(VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE)
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#define FDT_PCI_ADDR_CELLS 3
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#define FDT_PCI_INT_CELLS 1
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#define FDT_PLIC_ADDR_CELLS 0
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#define FDT_PLIC_INT_CELLS 1
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#define FDT_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + 1 + \
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FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS)
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#if defined(TARGET_RISCV32)
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#define VIRT_CPU TYPE_RISCV_CPU_BASE32
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#elif defined(TARGET_RISCV64)
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#define VIRT_CPU TYPE_RISCV_CPU_BASE64
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#endif
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#endif
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