450 lines
13 KiB
C
450 lines
13 KiB
C
/*
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* SuperH interrupt controller module
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*
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* Copyright (c) 2007 Magnus Damm
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* Based on sh_timer.c and arm_timer.c by Paul Brook
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* Copyright (c) 2005-2006 CodeSourcery.
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*
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* This code is licensed under the GPL.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "hw/sh4/sh_intc.h"
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#include "hw/irq.h"
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#include "hw/sh4/sh.h"
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#include "trace.h"
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void sh_intc_toggle_source(struct intc_source *source,
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int enable_adj, int assert_adj)
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{
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int enable_changed = 0;
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int pending_changed = 0;
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int old_pending;
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if (source->enable_count == source->enable_max && enable_adj == -1) {
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enable_changed = -1;
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}
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source->enable_count += enable_adj;
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if (source->enable_count == source->enable_max) {
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enable_changed = 1;
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}
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source->asserted += assert_adj;
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old_pending = source->pending;
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source->pending = source->asserted &&
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(source->enable_count == source->enable_max);
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if (old_pending != source->pending) {
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pending_changed = 1;
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}
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if (pending_changed) {
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if (source->pending) {
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source->parent->pending++;
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if (source->parent->pending == 1) {
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cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD);
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}
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} else {
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source->parent->pending--;
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if (source->parent->pending == 0) {
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cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD);
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}
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}
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}
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if (enable_changed || assert_adj || pending_changed) {
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trace_sh_intc_sources(source->parent->pending, source->asserted,
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source->enable_count, source->enable_max,
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source->vect, source->asserted ? "asserted " :
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assert_adj ? "deasserted" : "",
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enable_changed == 1 ? "enabled " :
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enable_changed == -1 ? "disabled " : "",
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source->pending ? "pending" : "");
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}
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}
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static void sh_intc_set_irq(void *opaque, int n, int level)
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{
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struct intc_desc *desc = opaque;
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struct intc_source *source = &desc->sources[n];
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if (level && !source->asserted) {
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sh_intc_toggle_source(source, 0, 1);
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} else if (!level && source->asserted) {
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sh_intc_toggle_source(source, 0, -1);
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}
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}
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int sh_intc_get_pending_vector(struct intc_desc *desc, int imask)
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{
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unsigned int i;
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/* slow: use a linked lists of pending sources instead */
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/* wrong: take interrupt priority into account (one list per priority) */
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if (imask == 0x0f) {
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return -1; /* FIXME, update code to include priority per source */
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}
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for (i = 0; i < desc->nr_sources; i++) {
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struct intc_source *source = &desc->sources[i];
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if (source->pending) {
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trace_sh_intc_pending(desc->pending, source->vect);
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return source->vect;
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}
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}
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g_assert_not_reached();
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}
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typedef enum {
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INTC_MODE_NONE,
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INTC_MODE_DUAL_SET,
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INTC_MODE_DUAL_CLR,
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INTC_MODE_ENABLE_REG,
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INTC_MODE_MASK_REG,
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} SHIntCMode;
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#define INTC_MODE_IS_PRIO 0x80
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static SHIntCMode sh_intc_mode(unsigned long address, unsigned long set_reg,
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unsigned long clr_reg)
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{
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if (address != A7ADDR(set_reg) && address != A7ADDR(clr_reg)) {
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return INTC_MODE_NONE;
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}
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if (set_reg && clr_reg) {
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return address == A7ADDR(set_reg) ?
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INTC_MODE_DUAL_SET : INTC_MODE_DUAL_CLR;
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}
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return set_reg ? INTC_MODE_ENABLE_REG : INTC_MODE_MASK_REG;
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}
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static void sh_intc_locate(struct intc_desc *desc,
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unsigned long address,
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unsigned long **datap,
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intc_enum **enums,
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unsigned int *first,
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unsigned int *width,
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unsigned int *modep)
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{
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SHIntCMode mode;
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unsigned int i;
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/* this is slow but works for now */
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if (desc->mask_regs) {
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for (i = 0; i < desc->nr_mask_regs; i++) {
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struct intc_mask_reg *mr = &desc->mask_regs[i];
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mode = sh_intc_mode(address, mr->set_reg, mr->clr_reg);
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if (mode != INTC_MODE_NONE) {
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*modep = mode;
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*datap = &mr->value;
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*enums = mr->enum_ids;
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*first = mr->reg_width - 1;
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*width = 1;
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return;
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}
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}
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}
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if (desc->prio_regs) {
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for (i = 0; i < desc->nr_prio_regs; i++) {
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struct intc_prio_reg *pr = &desc->prio_regs[i];
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mode = sh_intc_mode(address, pr->set_reg, pr->clr_reg);
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if (mode != INTC_MODE_NONE) {
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*modep = mode | INTC_MODE_IS_PRIO;
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*datap = &pr->value;
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*enums = pr->enum_ids;
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*first = pr->reg_width / pr->field_width - 1;
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*width = pr->field_width;
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return;
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}
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}
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}
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g_assert_not_reached();
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}
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static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id,
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int enable, int is_group)
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{
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struct intc_source *source = &desc->sources[id];
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if (!id) {
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return;
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}
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if (!source->next_enum_id && (!source->enable_max || !source->vect)) {
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qemu_log_mask(LOG_UNIMP,
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"sh_intc: reserved interrupt source %d modified\n", id);
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return;
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}
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if (source->vect) {
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sh_intc_toggle_source(source, enable ? 1 : -1, 0);
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}
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if ((is_group || !source->vect) && source->next_enum_id) {
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sh_intc_toggle_mask(desc, source->next_enum_id, enable, 1);
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}
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if (!source->vect) {
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trace_sh_intc_set(id, !!enable);
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}
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}
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static uint64_t sh_intc_read(void *opaque, hwaddr offset, unsigned size)
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{
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struct intc_desc *desc = opaque;
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intc_enum *enum_ids;
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unsigned int first;
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unsigned int width;
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unsigned int mode;
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unsigned long *valuep;
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sh_intc_locate(desc, (unsigned long)offset, &valuep,
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&enum_ids, &first, &width, &mode);
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trace_sh_intc_read(size, (uint64_t)offset, *valuep);
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return *valuep;
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}
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static void sh_intc_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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struct intc_desc *desc = opaque;
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intc_enum *enum_ids;
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unsigned int first;
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unsigned int width;
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unsigned int mode;
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unsigned long *valuep;
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unsigned int k;
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unsigned long mask;
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trace_sh_intc_write(size, (uint64_t)offset, value);
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sh_intc_locate(desc, (unsigned long)offset, &valuep,
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&enum_ids, &first, &width, &mode);
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switch (mode) {
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case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO:
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break;
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case INTC_MODE_DUAL_SET:
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value |= *valuep;
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break;
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case INTC_MODE_DUAL_CLR:
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value = *valuep & ~value;
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break;
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default:
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g_assert_not_reached();
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}
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for (k = 0; k <= first; k++) {
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mask = (1 << width) - 1;
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mask <<= (first - k) * width;
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if ((*valuep & mask) != (value & mask)) {
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sh_intc_toggle_mask(desc, enum_ids[k], value & mask, 0);
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}
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}
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*valuep = value;
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}
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static const MemoryRegionOps sh_intc_ops = {
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.read = sh_intc_read,
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.write = sh_intc_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void sh_intc_register_source(struct intc_desc *desc,
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intc_enum source,
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struct intc_group *groups,
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int nr_groups)
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{
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unsigned int i, k;
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intc_enum id;
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if (desc->mask_regs) {
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for (i = 0; i < desc->nr_mask_regs; i++) {
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struct intc_mask_reg *mr = &desc->mask_regs[i];
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for (k = 0; k < ARRAY_SIZE(mr->enum_ids); k++) {
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id = mr->enum_ids[k];
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if (id && id == source) {
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desc->sources[id].enable_max++;
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}
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}
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}
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}
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if (desc->prio_regs) {
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for (i = 0; i < desc->nr_prio_regs; i++) {
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struct intc_prio_reg *pr = &desc->prio_regs[i];
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for (k = 0; k < ARRAY_SIZE(pr->enum_ids); k++) {
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id = pr->enum_ids[k];
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if (id && id == source) {
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desc->sources[id].enable_max++;
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}
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}
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}
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}
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if (groups) {
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for (i = 0; i < nr_groups; i++) {
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struct intc_group *gr = &groups[i];
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for (k = 0; k < ARRAY_SIZE(gr->enum_ids); k++) {
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id = gr->enum_ids[k];
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if (id && id == source) {
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desc->sources[id].enable_max++;
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}
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}
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}
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}
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}
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void sh_intc_register_sources(struct intc_desc *desc,
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struct intc_vect *vectors,
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int nr_vectors,
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struct intc_group *groups,
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int nr_groups)
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{
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unsigned int i, k;
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intc_enum id;
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struct intc_source *s;
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for (i = 0; i < nr_vectors; i++) {
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struct intc_vect *vect = &vectors[i];
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sh_intc_register_source(desc, vect->enum_id, groups, nr_groups);
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id = vect->enum_id;
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if (id) {
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s = &desc->sources[id];
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s->vect = vect->vect;
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trace_sh_intc_register("source", vect->enum_id, s->vect,
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s->enable_count, s->enable_max);
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}
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}
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if (groups) {
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for (i = 0; i < nr_groups; i++) {
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struct intc_group *gr = &groups[i];
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id = gr->enum_id;
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s = &desc->sources[id];
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s->next_enum_id = gr->enum_ids[0];
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for (k = 1; k < ARRAY_SIZE(gr->enum_ids); k++) {
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if (gr->enum_ids[k]) {
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id = gr->enum_ids[k - 1];
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s = &desc->sources[id];
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s->next_enum_id = gr->enum_ids[k];
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}
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}
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trace_sh_intc_register("group", gr->enum_id, 0xffff,
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s->enable_count, s->enable_max);
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}
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}
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}
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static unsigned int sh_intc_register(MemoryRegion *sysmem,
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struct intc_desc *desc,
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const unsigned long address,
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const char *type,
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const char *action,
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const unsigned int index)
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{
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char name[60];
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MemoryRegion *iomem, *iomem_p4, *iomem_a7;
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if (!address) {
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return 0;
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}
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iomem = &desc->iomem;
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iomem_p4 = &desc->iomem_aliases[index];
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iomem_a7 = iomem_p4 + 1;
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snprintf(name, sizeof(name), "intc-%s-%s-%s", type, action, "p4");
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memory_region_init_alias(iomem_p4, NULL, name, iomem, A7ADDR(address), 4);
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memory_region_add_subregion(sysmem, P4ADDR(address), iomem_p4);
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snprintf(name, sizeof(name), "intc-%s-%s-%s", type, action, "a7");
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memory_region_init_alias(iomem_a7, NULL, name, iomem, A7ADDR(address), 4);
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memory_region_add_subregion(sysmem, A7ADDR(address), iomem_a7);
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/* used to increment aliases index */
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return 2;
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}
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int sh_intc_init(MemoryRegion *sysmem,
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struct intc_desc *desc,
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int nr_sources,
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struct intc_mask_reg *mask_regs,
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int nr_mask_regs,
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struct intc_prio_reg *prio_regs,
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int nr_prio_regs)
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{
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unsigned int i, j;
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desc->pending = 0;
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desc->nr_sources = nr_sources;
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desc->mask_regs = mask_regs;
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desc->nr_mask_regs = nr_mask_regs;
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desc->prio_regs = prio_regs;
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desc->nr_prio_regs = nr_prio_regs;
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/* Allocate 4 MemoryRegions per register (2 actions * 2 aliases) */
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desc->iomem_aliases = g_new0(MemoryRegion,
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(nr_mask_regs + nr_prio_regs) * 4);
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desc->sources = g_new0(struct intc_source, nr_sources);
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for (i = 0; i < nr_sources; i++) {
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desc->sources[i].parent = desc;
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}
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desc->irqs = qemu_allocate_irqs(sh_intc_set_irq, desc, nr_sources);
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memory_region_init_io(&desc->iomem, NULL, &sh_intc_ops, desc, "intc",
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0x100000000ULL);
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j = 0;
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if (desc->mask_regs) {
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for (i = 0; i < desc->nr_mask_regs; i++) {
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struct intc_mask_reg *mr = &desc->mask_regs[i];
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j += sh_intc_register(sysmem, desc, mr->set_reg, "mask", "set", j);
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j += sh_intc_register(sysmem, desc, mr->clr_reg, "mask", "clr", j);
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}
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}
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if (desc->prio_regs) {
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for (i = 0; i < desc->nr_prio_regs; i++) {
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struct intc_prio_reg *pr = &desc->prio_regs[i];
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j += sh_intc_register(sysmem, desc, pr->set_reg, "prio", "set", j);
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j += sh_intc_register(sysmem, desc, pr->clr_reg, "prio", "clr", j);
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}
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}
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return 0;
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}
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/*
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* Assert level <n> IRL interrupt.
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* 0:deassert. 1:lowest priority,... 15:highest priority
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*/
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void sh_intc_set_irl(void *opaque, int n, int level)
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{
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struct intc_source *s = opaque;
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int i, irl = level ^ 15;
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intc_enum id = s->next_enum_id;
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for (i = 0; id; id = s->next_enum_id, i++) {
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s = &s->parent->sources[id];
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if (i == irl) {
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sh_intc_toggle_source(s, s->enable_count ? 0 : 1,
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s->asserted ? 0 : 1);
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} else if (s->asserted) {
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sh_intc_toggle_source(s, 0, -1);
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}
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}
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}
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