Yoshinori Sato 27a4a30e29 target/rx: CPU definitions ... Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> [PMD: Use newer QOM style, split cpu-qom.h, restrict access to extable array, use rx_cpu_tlb_fill() extracted from patch of Yoshinori Sato 'Convert to CPUClass::tlb_fill', call cpu_reset after qemu_init_vcpu, make rx_crname a function] Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20200224141923.82118-7-ysato@users.sourceforge.jp> Acked-by: Richard Henderson <richard.henderson@linaro.org> [PMD: Use GByteArray in gdbstub (rebase commit a010bdbe), use device_class_set_parent_reset (rebase commit 781c67ca)] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>		2020-03-19 17:58:05 +01:00
..
aarch64-core.xml
aarch64-fpu.xml
arm-core.xml
arm-neon.xml
arm-vfp3.xml
arm-vfp.xml
cf-core.xml
cf-fp.xml
i386-32bit.xml	gdbstub: Fix i386/x86_64 machine description and add control registers	2019-02-05 16:50:18 +01:00
i386-64bit.xml	gdbstub: Fix i386/x86_64 machine description and add control registers	2019-02-05 16:50:18 +01:00
m68k-fp.xml	target-m68k: define 96bit FP registers for gdb on 680x0	2017-06-21 22:11:12 +02:00
power64-core.xml
power-altivec.xml
power-core.xml
power-fpu.xml
power-spe.xml
power-vsx.xml
riscv-32bit-cpu.xml	RISC-V: Add 32-bit gdb xml files.	2019-03-19 05:13:24 -07:00
riscv-32bit-csr.xml	RISC-V: Add 32-bit gdb xml files.	2019-03-19 05:13:24 -07:00
riscv-32bit-fpu.xml	RISC-V: Add 64-bit gdb xml files.	2019-03-19 05:13:24 -07:00
riscv-32bit-virtual.xml	target/riscv: Expose "priv" register for GDB for reads	2019-10-28 07:47:29 -07:00
riscv-64bit-cpu.xml	RISC-V: Add 64-bit gdb xml files.	2019-03-19 05:13:24 -07:00
riscv-64bit-csr.xml	RISC-V: Add 64-bit gdb xml files.	2019-03-19 05:13:24 -07:00
riscv-64bit-fpu.xml	RISC-V: Add 64-bit gdb xml files.	2019-03-19 05:13:24 -07:00
riscv-64bit-virtual.xml	target/riscv: Expose "priv" register for GDB for reads	2019-10-28 07:47:29 -07:00
rx-core.xml	target/rx: CPU definitions	2020-03-19 17:58:05 +01:00
s390-acr.xml
s390-cr.xml
s390-fpr.xml
s390-gs.xml	s390x/gdb: add gs registers	2017-07-14 12:29:49 +02:00
s390-virt.xml
s390-vx.xml
s390x-core64.xml