qemu-e2k/disas
Philipp Tomsich 3de1fb712a target/riscv: update disas.c for xnor/orn/andn and slli.uw
The decoding of the following instructions from Zb[abcs] currently
contains decoding/printing errors:
 * xnor,orn,andn: the rs2 operand is not being printed
 * slli.uw: decodes and prints the immediate shift-amount as a
            register (e.g. 'shift-by-2' becomes 'sp') instead of
	    interpreting this as an immediate

This commit updates the instruction descriptions to use the
appropriate decoding/printing formats.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230120151551.1022761-1-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-02-07 08:19:22 +10:00
..
alpha.c
capstone.c disas: use result of ->read_memory_func 2022-10-06 11:53:40 +01:00
cris.c
hexagon.c Hexagon (disas/hexagon.c) fix memory leak for early exit cases 2021-08-12 09:06:05 -05:00
hppa.c disas/: fix some comment spelling errors 2020-09-17 20:40:08 +02:00
m68k.c disas/: fix some comment spelling errors 2020-09-17 20:40:08 +02:00
meson.build mips: Always include nanomips disassembler 2023-01-13 16:22:53 +01:00
microblaze.c
mips.c disas/mips: Fix branch displacement for BEQZC and BNEZC 2022-10-31 11:32:07 +01:00
nanomips.c disas/nanomips: Tidy read for 48-bit opcodes 2022-11-08 01:04:25 +01:00
nios2.c disas/nios2: Simplify endianess conversion 2021-10-22 18:07:30 +02:00
riscv.c target/riscv: update disas.c for xnor/orn/andn and slli.uw 2023-02-07 08:19:22 +10:00
sh4.c
sparc.c
xtensa.c