918 lines
26 KiB
C
918 lines
26 KiB
C
/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2009, 2011 Stefan Weil
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "tcg-be-null.h"
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/* TODO list:
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* - See TODO comments in code.
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*/
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/* Marker for missing code. */
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#define TODO() \
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do { \
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fprintf(stderr, "TODO %s:%u: %s()\n", \
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__FILE__, __LINE__, __func__); \
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tcg_abort(); \
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} while (0)
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/* Bitfield n...m (in 32 bit value). */
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#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
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/* Macros used in tcg_target_op_defs. */
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#define R "r"
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#define RI "ri"
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#if TCG_TARGET_REG_BITS == 32
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# define R64 "r", "r"
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#else
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# define R64 "r"
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#endif
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#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
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# define L "L", "L"
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# define S "S", "S"
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#else
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# define L "L"
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# define S "S"
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#endif
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/* TODO: documentation. */
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static const TCGTargetOpDef tcg_target_op_defs[] = {
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{ INDEX_op_exit_tb, { NULL } },
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{ INDEX_op_goto_tb, { NULL } },
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{ INDEX_op_call, { RI } },
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{ INDEX_op_br, { NULL } },
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{ INDEX_op_mov_i32, { R, R } },
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{ INDEX_op_movi_i32, { R } },
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{ INDEX_op_ld8u_i32, { R, R } },
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{ INDEX_op_ld8s_i32, { R, R } },
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{ INDEX_op_ld16u_i32, { R, R } },
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{ INDEX_op_ld16s_i32, { R, R } },
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{ INDEX_op_ld_i32, { R, R } },
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{ INDEX_op_st8_i32, { R, R } },
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{ INDEX_op_st16_i32, { R, R } },
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{ INDEX_op_st_i32, { R, R } },
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{ INDEX_op_add_i32, { R, RI, RI } },
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{ INDEX_op_sub_i32, { R, RI, RI } },
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{ INDEX_op_mul_i32, { R, RI, RI } },
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#if TCG_TARGET_HAS_div_i32
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{ INDEX_op_div_i32, { R, R, R } },
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{ INDEX_op_divu_i32, { R, R, R } },
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{ INDEX_op_rem_i32, { R, R, R } },
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{ INDEX_op_remu_i32, { R, R, R } },
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#elif TCG_TARGET_HAS_div2_i32
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{ INDEX_op_div2_i32, { R, R, "0", "1", R } },
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{ INDEX_op_divu2_i32, { R, R, "0", "1", R } },
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#endif
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/* TODO: Does R, RI, RI result in faster code than R, R, RI?
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If both operands are constants, we can optimize. */
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{ INDEX_op_and_i32, { R, RI, RI } },
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#if TCG_TARGET_HAS_andc_i32
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{ INDEX_op_andc_i32, { R, RI, RI } },
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#endif
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#if TCG_TARGET_HAS_eqv_i32
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{ INDEX_op_eqv_i32, { R, RI, RI } },
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#endif
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#if TCG_TARGET_HAS_nand_i32
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{ INDEX_op_nand_i32, { R, RI, RI } },
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#endif
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#if TCG_TARGET_HAS_nor_i32
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{ INDEX_op_nor_i32, { R, RI, RI } },
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#endif
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{ INDEX_op_or_i32, { R, RI, RI } },
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#if TCG_TARGET_HAS_orc_i32
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{ INDEX_op_orc_i32, { R, RI, RI } },
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#endif
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{ INDEX_op_xor_i32, { R, RI, RI } },
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{ INDEX_op_shl_i32, { R, RI, RI } },
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{ INDEX_op_shr_i32, { R, RI, RI } },
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{ INDEX_op_sar_i32, { R, RI, RI } },
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#if TCG_TARGET_HAS_rot_i32
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{ INDEX_op_rotl_i32, { R, RI, RI } },
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{ INDEX_op_rotr_i32, { R, RI, RI } },
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#endif
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#if TCG_TARGET_HAS_deposit_i32
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{ INDEX_op_deposit_i32, { R, "0", R } },
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#endif
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{ INDEX_op_brcond_i32, { R, RI } },
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{ INDEX_op_setcond_i32, { R, R, RI } },
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#if TCG_TARGET_REG_BITS == 64
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{ INDEX_op_setcond_i64, { R, R, RI } },
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#endif /* TCG_TARGET_REG_BITS == 64 */
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#if TCG_TARGET_REG_BITS == 32
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/* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
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{ INDEX_op_add2_i32, { R, R, R, R, R, R } },
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{ INDEX_op_sub2_i32, { R, R, R, R, R, R } },
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{ INDEX_op_brcond2_i32, { R, R, RI, RI } },
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{ INDEX_op_mulu2_i32, { R, R, R, R } },
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{ INDEX_op_setcond2_i32, { R, R, R, RI, RI } },
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#endif
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#if TCG_TARGET_HAS_not_i32
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{ INDEX_op_not_i32, { R, R } },
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#endif
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#if TCG_TARGET_HAS_neg_i32
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{ INDEX_op_neg_i32, { R, R } },
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#endif
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#if TCG_TARGET_REG_BITS == 64
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{ INDEX_op_mov_i64, { R, R } },
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{ INDEX_op_movi_i64, { R } },
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{ INDEX_op_ld8u_i64, { R, R } },
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{ INDEX_op_ld8s_i64, { R, R } },
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{ INDEX_op_ld16u_i64, { R, R } },
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{ INDEX_op_ld16s_i64, { R, R } },
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{ INDEX_op_ld32u_i64, { R, R } },
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{ INDEX_op_ld32s_i64, { R, R } },
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{ INDEX_op_ld_i64, { R, R } },
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{ INDEX_op_st8_i64, { R, R } },
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{ INDEX_op_st16_i64, { R, R } },
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{ INDEX_op_st32_i64, { R, R } },
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{ INDEX_op_st_i64, { R, R } },
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{ INDEX_op_add_i64, { R, RI, RI } },
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{ INDEX_op_sub_i64, { R, RI, RI } },
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{ INDEX_op_mul_i64, { R, RI, RI } },
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#if TCG_TARGET_HAS_div_i64
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{ INDEX_op_div_i64, { R, R, R } },
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{ INDEX_op_divu_i64, { R, R, R } },
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{ INDEX_op_rem_i64, { R, R, R } },
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{ INDEX_op_remu_i64, { R, R, R } },
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#elif TCG_TARGET_HAS_div2_i64
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{ INDEX_op_div2_i64, { R, R, "0", "1", R } },
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{ INDEX_op_divu2_i64, { R, R, "0", "1", R } },
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#endif
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{ INDEX_op_and_i64, { R, RI, RI } },
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#if TCG_TARGET_HAS_andc_i64
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{ INDEX_op_andc_i64, { R, RI, RI } },
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#endif
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#if TCG_TARGET_HAS_eqv_i64
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{ INDEX_op_eqv_i64, { R, RI, RI } },
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#endif
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#if TCG_TARGET_HAS_nand_i64
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{ INDEX_op_nand_i64, { R, RI, RI } },
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#endif
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#if TCG_TARGET_HAS_nor_i64
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{ INDEX_op_nor_i64, { R, RI, RI } },
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#endif
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{ INDEX_op_or_i64, { R, RI, RI } },
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#if TCG_TARGET_HAS_orc_i64
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{ INDEX_op_orc_i64, { R, RI, RI } },
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#endif
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{ INDEX_op_xor_i64, { R, RI, RI } },
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{ INDEX_op_shl_i64, { R, RI, RI } },
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{ INDEX_op_shr_i64, { R, RI, RI } },
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{ INDEX_op_sar_i64, { R, RI, RI } },
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#if TCG_TARGET_HAS_rot_i64
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{ INDEX_op_rotl_i64, { R, RI, RI } },
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{ INDEX_op_rotr_i64, { R, RI, RI } },
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#endif
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#if TCG_TARGET_HAS_deposit_i64
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{ INDEX_op_deposit_i64, { R, "0", R } },
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#endif
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{ INDEX_op_brcond_i64, { R, RI } },
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#if TCG_TARGET_HAS_ext8s_i64
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{ INDEX_op_ext8s_i64, { R, R } },
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#endif
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#if TCG_TARGET_HAS_ext16s_i64
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{ INDEX_op_ext16s_i64, { R, R } },
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#endif
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#if TCG_TARGET_HAS_ext32s_i64
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{ INDEX_op_ext32s_i64, { R, R } },
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#endif
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#if TCG_TARGET_HAS_ext8u_i64
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{ INDEX_op_ext8u_i64, { R, R } },
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#endif
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#if TCG_TARGET_HAS_ext16u_i64
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{ INDEX_op_ext16u_i64, { R, R } },
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#endif
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#if TCG_TARGET_HAS_ext32u_i64
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{ INDEX_op_ext32u_i64, { R, R } },
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#endif
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#if TCG_TARGET_HAS_bswap16_i64
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{ INDEX_op_bswap16_i64, { R, R } },
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#endif
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#if TCG_TARGET_HAS_bswap32_i64
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{ INDEX_op_bswap32_i64, { R, R } },
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#endif
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#if TCG_TARGET_HAS_bswap64_i64
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{ INDEX_op_bswap64_i64, { R, R } },
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#endif
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#if TCG_TARGET_HAS_not_i64
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{ INDEX_op_not_i64, { R, R } },
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#endif
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#if TCG_TARGET_HAS_neg_i64
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{ INDEX_op_neg_i64, { R, R } },
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#endif
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#endif /* TCG_TARGET_REG_BITS == 64 */
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{ INDEX_op_qemu_ld8u, { R, L } },
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{ INDEX_op_qemu_ld8s, { R, L } },
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{ INDEX_op_qemu_ld16u, { R, L } },
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{ INDEX_op_qemu_ld16s, { R, L } },
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{ INDEX_op_qemu_ld32, { R, L } },
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#if TCG_TARGET_REG_BITS == 64
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{ INDEX_op_qemu_ld32u, { R, L } },
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{ INDEX_op_qemu_ld32s, { R, L } },
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#endif
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{ INDEX_op_qemu_ld64, { R64, L } },
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{ INDEX_op_qemu_st8, { R, S } },
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{ INDEX_op_qemu_st16, { R, S } },
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{ INDEX_op_qemu_st32, { R, S } },
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{ INDEX_op_qemu_st64, { R64, S } },
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#if TCG_TARGET_HAS_ext8s_i32
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{ INDEX_op_ext8s_i32, { R, R } },
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#endif
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#if TCG_TARGET_HAS_ext16s_i32
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{ INDEX_op_ext16s_i32, { R, R } },
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#endif
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#if TCG_TARGET_HAS_ext8u_i32
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{ INDEX_op_ext8u_i32, { R, R } },
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#endif
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#if TCG_TARGET_HAS_ext16u_i32
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{ INDEX_op_ext16u_i32, { R, R } },
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#endif
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#if TCG_TARGET_HAS_bswap16_i32
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{ INDEX_op_bswap16_i32, { R, R } },
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#endif
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#if TCG_TARGET_HAS_bswap32_i32
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{ INDEX_op_bswap32_i32, { R, R } },
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#endif
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{ -1 },
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};
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static const int tcg_target_reg_alloc_order[] = {
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TCG_REG_R0,
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TCG_REG_R1,
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TCG_REG_R2,
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TCG_REG_R3,
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#if 0 /* used for TCG_REG_CALL_STACK */
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TCG_REG_R4,
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#endif
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TCG_REG_R5,
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TCG_REG_R6,
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TCG_REG_R7,
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#if TCG_TARGET_NB_REGS >= 16
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TCG_REG_R8,
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TCG_REG_R9,
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TCG_REG_R10,
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TCG_REG_R11,
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TCG_REG_R12,
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TCG_REG_R13,
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TCG_REG_R14,
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TCG_REG_R15,
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#endif
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};
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#if MAX_OPC_PARAM_IARGS != 5
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# error Fix needed, number of supported input arguments changed!
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#endif
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static const int tcg_target_call_iarg_regs[] = {
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TCG_REG_R0,
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TCG_REG_R1,
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TCG_REG_R2,
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TCG_REG_R3,
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#if 0 /* used for TCG_REG_CALL_STACK */
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TCG_REG_R4,
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#endif
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TCG_REG_R5,
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#if TCG_TARGET_REG_BITS == 32
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/* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
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TCG_REG_R6,
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TCG_REG_R7,
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#if TCG_TARGET_NB_REGS >= 16
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TCG_REG_R8,
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TCG_REG_R9,
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TCG_REG_R10,
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#else
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# error Too few input registers available
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#endif
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#endif
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};
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static const int tcg_target_call_oarg_regs[] = {
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TCG_REG_R0,
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#if TCG_TARGET_REG_BITS == 32
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TCG_REG_R1
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#endif
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};
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#ifndef NDEBUG
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static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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"r00",
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"r01",
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"r02",
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"r03",
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"r04",
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"r05",
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"r06",
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"r07",
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#if TCG_TARGET_NB_REGS >= 16
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"r08",
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"r09",
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"r10",
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"r11",
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"r12",
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"r13",
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"r14",
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"r15",
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#if TCG_TARGET_NB_REGS >= 32
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"r16",
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"r17",
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"r18",
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"r19",
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"r20",
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"r21",
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"r22",
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"r23",
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"r24",
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"r25",
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"r26",
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"r27",
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"r28",
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"r29",
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"r30",
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"r31"
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#endif
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#endif
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};
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#endif
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static void patch_reloc(tcg_insn_unit *code_ptr, int type,
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intptr_t value, intptr_t addend)
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{
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/* tcg_out_reloc always uses the same type, addend. */
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assert(type == sizeof(tcg_target_long));
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assert(addend == 0);
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assert(value != 0);
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if (TCG_TARGET_REG_BITS == 32) {
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tcg_patch32(code_ptr, value);
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} else {
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tcg_patch64(code_ptr, value);
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}
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}
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/* Parse target specific constraints. */
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static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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{
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const char *ct_str = *pct_str;
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switch (ct_str[0]) {
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case 'r':
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case 'L': /* qemu_ld constraint */
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case 'S': /* qemu_st constraint */
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ct->ct |= TCG_CT_REG;
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tcg_regset_set32(ct->u.regs, 0, BIT(TCG_TARGET_NB_REGS) - 1);
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break;
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default:
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return -1;
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}
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ct_str++;
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*pct_str = ct_str;
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return 0;
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}
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#if defined(CONFIG_DEBUG_TCG_INTERPRETER)
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/* Show current bytecode. Used by tcg interpreter. */
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void tci_disas(uint8_t opc)
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{
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const TCGOpDef *def = &tcg_op_defs[opc];
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fprintf(stderr, "TCG %s %u, %u, %u\n",
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def->name, def->nb_oargs, def->nb_iargs, def->nb_cargs);
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}
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#endif
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/* Write value (native size). */
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static void tcg_out_i(TCGContext *s, tcg_target_ulong v)
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{
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if (TCG_TARGET_REG_BITS == 32) {
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tcg_out32(s, v);
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} else {
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tcg_out64(s, v);
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}
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}
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/* Write opcode. */
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static void tcg_out_op_t(TCGContext *s, TCGOpcode op)
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{
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tcg_out8(s, op);
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tcg_out8(s, 0);
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}
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/* Write register. */
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static void tcg_out_r(TCGContext *s, TCGArg t0)
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{
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assert(t0 < TCG_TARGET_NB_REGS);
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tcg_out8(s, t0);
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}
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/* Write register or constant (native size). */
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static void tcg_out_ri(TCGContext *s, int const_arg, TCGArg arg)
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{
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if (const_arg) {
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assert(const_arg == 1);
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tcg_out8(s, TCG_CONST);
|
|
tcg_out_i(s, arg);
|
|
} else {
|
|
tcg_out_r(s, arg);
|
|
}
|
|
}
|
|
|
|
/* Write register or constant (32 bit). */
|
|
static void tcg_out_ri32(TCGContext *s, int const_arg, TCGArg arg)
|
|
{
|
|
if (const_arg) {
|
|
assert(const_arg == 1);
|
|
tcg_out8(s, TCG_CONST);
|
|
tcg_out32(s, arg);
|
|
} else {
|
|
tcg_out_r(s, arg);
|
|
}
|
|
}
|
|
|
|
#if TCG_TARGET_REG_BITS == 64
|
|
/* Write register or constant (64 bit). */
|
|
static void tcg_out_ri64(TCGContext *s, int const_arg, TCGArg arg)
|
|
{
|
|
if (const_arg) {
|
|
assert(const_arg == 1);
|
|
tcg_out8(s, TCG_CONST);
|
|
tcg_out64(s, arg);
|
|
} else {
|
|
tcg_out_r(s, arg);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/* Write label. */
|
|
static void tci_out_label(TCGContext *s, TCGArg arg)
|
|
{
|
|
TCGLabel *label = &s->labels[arg];
|
|
if (label->has_value) {
|
|
tcg_out_i(s, label->u.value);
|
|
assert(label->u.value);
|
|
} else {
|
|
tcg_out_reloc(s, s->code_ptr, sizeof(tcg_target_ulong), arg, 0);
|
|
s->code_ptr += sizeof(tcg_target_ulong);
|
|
}
|
|
}
|
|
|
|
static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
|
|
intptr_t arg2)
|
|
{
|
|
uint8_t *old_code_ptr = s->code_ptr;
|
|
if (type == TCG_TYPE_I32) {
|
|
tcg_out_op_t(s, INDEX_op_ld_i32);
|
|
tcg_out_r(s, ret);
|
|
tcg_out_r(s, arg1);
|
|
tcg_out32(s, arg2);
|
|
} else {
|
|
assert(type == TCG_TYPE_I64);
|
|
#if TCG_TARGET_REG_BITS == 64
|
|
tcg_out_op_t(s, INDEX_op_ld_i64);
|
|
tcg_out_r(s, ret);
|
|
tcg_out_r(s, arg1);
|
|
assert(arg2 == (int32_t)arg2);
|
|
tcg_out32(s, arg2);
|
|
#else
|
|
TODO();
|
|
#endif
|
|
}
|
|
old_code_ptr[1] = s->code_ptr - old_code_ptr;
|
|
}
|
|
|
|
static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
|
|
{
|
|
uint8_t *old_code_ptr = s->code_ptr;
|
|
assert(ret != arg);
|
|
#if TCG_TARGET_REG_BITS == 32
|
|
tcg_out_op_t(s, INDEX_op_mov_i32);
|
|
#else
|
|
tcg_out_op_t(s, INDEX_op_mov_i64);
|
|
#endif
|
|
tcg_out_r(s, ret);
|
|
tcg_out_r(s, arg);
|
|
old_code_ptr[1] = s->code_ptr - old_code_ptr;
|
|
}
|
|
|
|
static void tcg_out_movi(TCGContext *s, TCGType type,
|
|
TCGReg t0, tcg_target_long arg)
|
|
{
|
|
uint8_t *old_code_ptr = s->code_ptr;
|
|
uint32_t arg32 = arg;
|
|
if (type == TCG_TYPE_I32 || arg == arg32) {
|
|
tcg_out_op_t(s, INDEX_op_movi_i32);
|
|
tcg_out_r(s, t0);
|
|
tcg_out32(s, arg32);
|
|
} else {
|
|
assert(type == TCG_TYPE_I64);
|
|
#if TCG_TARGET_REG_BITS == 64
|
|
tcg_out_op_t(s, INDEX_op_movi_i64);
|
|
tcg_out_r(s, t0);
|
|
tcg_out64(s, arg);
|
|
#else
|
|
TODO();
|
|
#endif
|
|
}
|
|
old_code_ptr[1] = s->code_ptr - old_code_ptr;
|
|
}
|
|
|
|
static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *arg)
|
|
{
|
|
tcg_out_ri(s, 1, (uintptr_t)arg);
|
|
}
|
|
|
|
static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
|
|
const int *const_args)
|
|
{
|
|
uint8_t *old_code_ptr = s->code_ptr;
|
|
|
|
tcg_out_op_t(s, opc);
|
|
|
|
switch (opc) {
|
|
case INDEX_op_exit_tb:
|
|
tcg_out64(s, args[0]);
|
|
break;
|
|
case INDEX_op_goto_tb:
|
|
if (s->tb_jmp_offset) {
|
|
/* Direct jump method. */
|
|
assert(args[0] < ARRAY_SIZE(s->tb_jmp_offset));
|
|
s->tb_jmp_offset[args[0]] = tcg_current_code_size(s);
|
|
tcg_out32(s, 0);
|
|
} else {
|
|
/* Indirect jump method. */
|
|
TODO();
|
|
}
|
|
assert(args[0] < ARRAY_SIZE(s->tb_next_offset));
|
|
s->tb_next_offset[args[0]] = tcg_current_code_size(s);
|
|
break;
|
|
case INDEX_op_br:
|
|
tci_out_label(s, args[0]);
|
|
break;
|
|
case INDEX_op_call:
|
|
tcg_out_ri(s, const_args[0], args[0]);
|
|
break;
|
|
case INDEX_op_setcond_i32:
|
|
tcg_out_r(s, args[0]);
|
|
tcg_out_r(s, args[1]);
|
|
tcg_out_ri32(s, const_args[2], args[2]);
|
|
tcg_out8(s, args[3]); /* condition */
|
|
break;
|
|
#if TCG_TARGET_REG_BITS == 32
|
|
case INDEX_op_setcond2_i32:
|
|
/* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */
|
|
tcg_out_r(s, args[0]);
|
|
tcg_out_r(s, args[1]);
|
|
tcg_out_r(s, args[2]);
|
|
tcg_out_ri32(s, const_args[3], args[3]);
|
|
tcg_out_ri32(s, const_args[4], args[4]);
|
|
tcg_out8(s, args[5]); /* condition */
|
|
break;
|
|
#elif TCG_TARGET_REG_BITS == 64
|
|
case INDEX_op_setcond_i64:
|
|
tcg_out_r(s, args[0]);
|
|
tcg_out_r(s, args[1]);
|
|
tcg_out_ri64(s, const_args[2], args[2]);
|
|
tcg_out8(s, args[3]); /* condition */
|
|
break;
|
|
#endif
|
|
case INDEX_op_movi_i32:
|
|
TODO(); /* Handled by tcg_out_movi? */
|
|
break;
|
|
case INDEX_op_ld8u_i32:
|
|
case INDEX_op_ld8s_i32:
|
|
case INDEX_op_ld16u_i32:
|
|
case INDEX_op_ld16s_i32:
|
|
case INDEX_op_ld_i32:
|
|
case INDEX_op_st8_i32:
|
|
case INDEX_op_st16_i32:
|
|
case INDEX_op_st_i32:
|
|
case INDEX_op_ld8u_i64:
|
|
case INDEX_op_ld8s_i64:
|
|
case INDEX_op_ld16u_i64:
|
|
case INDEX_op_ld16s_i64:
|
|
case INDEX_op_ld32u_i64:
|
|
case INDEX_op_ld32s_i64:
|
|
case INDEX_op_ld_i64:
|
|
case INDEX_op_st8_i64:
|
|
case INDEX_op_st16_i64:
|
|
case INDEX_op_st32_i64:
|
|
case INDEX_op_st_i64:
|
|
tcg_out_r(s, args[0]);
|
|
tcg_out_r(s, args[1]);
|
|
assert(args[2] == (int32_t)args[2]);
|
|
tcg_out32(s, args[2]);
|
|
break;
|
|
case INDEX_op_add_i32:
|
|
case INDEX_op_sub_i32:
|
|
case INDEX_op_mul_i32:
|
|
case INDEX_op_and_i32:
|
|
case INDEX_op_andc_i32: /* Optional (TCG_TARGET_HAS_andc_i32). */
|
|
case INDEX_op_eqv_i32: /* Optional (TCG_TARGET_HAS_eqv_i32). */
|
|
case INDEX_op_nand_i32: /* Optional (TCG_TARGET_HAS_nand_i32). */
|
|
case INDEX_op_nor_i32: /* Optional (TCG_TARGET_HAS_nor_i32). */
|
|
case INDEX_op_or_i32:
|
|
case INDEX_op_orc_i32: /* Optional (TCG_TARGET_HAS_orc_i32). */
|
|
case INDEX_op_xor_i32:
|
|
case INDEX_op_shl_i32:
|
|
case INDEX_op_shr_i32:
|
|
case INDEX_op_sar_i32:
|
|
case INDEX_op_rotl_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */
|
|
case INDEX_op_rotr_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */
|
|
tcg_out_r(s, args[0]);
|
|
tcg_out_ri32(s, const_args[1], args[1]);
|
|
tcg_out_ri32(s, const_args[2], args[2]);
|
|
break;
|
|
case INDEX_op_deposit_i32: /* Optional (TCG_TARGET_HAS_deposit_i32). */
|
|
tcg_out_r(s, args[0]);
|
|
tcg_out_r(s, args[1]);
|
|
tcg_out_r(s, args[2]);
|
|
assert(args[3] <= UINT8_MAX);
|
|
tcg_out8(s, args[3]);
|
|
assert(args[4] <= UINT8_MAX);
|
|
tcg_out8(s, args[4]);
|
|
break;
|
|
|
|
#if TCG_TARGET_REG_BITS == 64
|
|
case INDEX_op_mov_i64:
|
|
case INDEX_op_movi_i64:
|
|
TODO();
|
|
break;
|
|
case INDEX_op_add_i64:
|
|
case INDEX_op_sub_i64:
|
|
case INDEX_op_mul_i64:
|
|
case INDEX_op_and_i64:
|
|
case INDEX_op_andc_i64: /* Optional (TCG_TARGET_HAS_andc_i64). */
|
|
case INDEX_op_eqv_i64: /* Optional (TCG_TARGET_HAS_eqv_i64). */
|
|
case INDEX_op_nand_i64: /* Optional (TCG_TARGET_HAS_nand_i64). */
|
|
case INDEX_op_nor_i64: /* Optional (TCG_TARGET_HAS_nor_i64). */
|
|
case INDEX_op_or_i64:
|
|
case INDEX_op_orc_i64: /* Optional (TCG_TARGET_HAS_orc_i64). */
|
|
case INDEX_op_xor_i64:
|
|
case INDEX_op_shl_i64:
|
|
case INDEX_op_shr_i64:
|
|
case INDEX_op_sar_i64:
|
|
case INDEX_op_rotl_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */
|
|
case INDEX_op_rotr_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */
|
|
tcg_out_r(s, args[0]);
|
|
tcg_out_ri64(s, const_args[1], args[1]);
|
|
tcg_out_ri64(s, const_args[2], args[2]);
|
|
break;
|
|
case INDEX_op_deposit_i64: /* Optional (TCG_TARGET_HAS_deposit_i64). */
|
|
tcg_out_r(s, args[0]);
|
|
tcg_out_r(s, args[1]);
|
|
tcg_out_r(s, args[2]);
|
|
assert(args[3] <= UINT8_MAX);
|
|
tcg_out8(s, args[3]);
|
|
assert(args[4] <= UINT8_MAX);
|
|
tcg_out8(s, args[4]);
|
|
break;
|
|
case INDEX_op_div_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
|
|
case INDEX_op_divu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
|
|
case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
|
|
case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
|
|
TODO();
|
|
break;
|
|
case INDEX_op_div2_i64: /* Optional (TCG_TARGET_HAS_div2_i64). */
|
|
case INDEX_op_divu2_i64: /* Optional (TCG_TARGET_HAS_div2_i64). */
|
|
TODO();
|
|
break;
|
|
case INDEX_op_brcond_i64:
|
|
tcg_out_r(s, args[0]);
|
|
tcg_out_ri64(s, const_args[1], args[1]);
|
|
tcg_out8(s, args[2]); /* condition */
|
|
tci_out_label(s, args[3]);
|
|
break;
|
|
case INDEX_op_bswap16_i64: /* Optional (TCG_TARGET_HAS_bswap16_i64). */
|
|
case INDEX_op_bswap32_i64: /* Optional (TCG_TARGET_HAS_bswap32_i64). */
|
|
case INDEX_op_bswap64_i64: /* Optional (TCG_TARGET_HAS_bswap64_i64). */
|
|
case INDEX_op_not_i64: /* Optional (TCG_TARGET_HAS_not_i64). */
|
|
case INDEX_op_neg_i64: /* Optional (TCG_TARGET_HAS_neg_i64). */
|
|
case INDEX_op_ext8s_i64: /* Optional (TCG_TARGET_HAS_ext8s_i64). */
|
|
case INDEX_op_ext8u_i64: /* Optional (TCG_TARGET_HAS_ext8u_i64). */
|
|
case INDEX_op_ext16s_i64: /* Optional (TCG_TARGET_HAS_ext16s_i64). */
|
|
case INDEX_op_ext16u_i64: /* Optional (TCG_TARGET_HAS_ext16u_i64). */
|
|
case INDEX_op_ext32s_i64: /* Optional (TCG_TARGET_HAS_ext32s_i64). */
|
|
case INDEX_op_ext32u_i64: /* Optional (TCG_TARGET_HAS_ext32u_i64). */
|
|
#endif /* TCG_TARGET_REG_BITS == 64 */
|
|
case INDEX_op_neg_i32: /* Optional (TCG_TARGET_HAS_neg_i32). */
|
|
case INDEX_op_not_i32: /* Optional (TCG_TARGET_HAS_not_i32). */
|
|
case INDEX_op_ext8s_i32: /* Optional (TCG_TARGET_HAS_ext8s_i32). */
|
|
case INDEX_op_ext16s_i32: /* Optional (TCG_TARGET_HAS_ext16s_i32). */
|
|
case INDEX_op_ext8u_i32: /* Optional (TCG_TARGET_HAS_ext8u_i32). */
|
|
case INDEX_op_ext16u_i32: /* Optional (TCG_TARGET_HAS_ext16u_i32). */
|
|
case INDEX_op_bswap16_i32: /* Optional (TCG_TARGET_HAS_bswap16_i32). */
|
|
case INDEX_op_bswap32_i32: /* Optional (TCG_TARGET_HAS_bswap32_i32). */
|
|
tcg_out_r(s, args[0]);
|
|
tcg_out_r(s, args[1]);
|
|
break;
|
|
case INDEX_op_div_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
|
|
case INDEX_op_divu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
|
|
case INDEX_op_rem_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
|
|
case INDEX_op_remu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
|
|
tcg_out_r(s, args[0]);
|
|
tcg_out_ri32(s, const_args[1], args[1]);
|
|
tcg_out_ri32(s, const_args[2], args[2]);
|
|
break;
|
|
case INDEX_op_div2_i32: /* Optional (TCG_TARGET_HAS_div2_i32). */
|
|
case INDEX_op_divu2_i32: /* Optional (TCG_TARGET_HAS_div2_i32). */
|
|
TODO();
|
|
break;
|
|
#if TCG_TARGET_REG_BITS == 32
|
|
case INDEX_op_add2_i32:
|
|
case INDEX_op_sub2_i32:
|
|
tcg_out_r(s, args[0]);
|
|
tcg_out_r(s, args[1]);
|
|
tcg_out_r(s, args[2]);
|
|
tcg_out_r(s, args[3]);
|
|
tcg_out_r(s, args[4]);
|
|
tcg_out_r(s, args[5]);
|
|
break;
|
|
case INDEX_op_brcond2_i32:
|
|
tcg_out_r(s, args[0]);
|
|
tcg_out_r(s, args[1]);
|
|
tcg_out_ri32(s, const_args[2], args[2]);
|
|
tcg_out_ri32(s, const_args[3], args[3]);
|
|
tcg_out8(s, args[4]); /* condition */
|
|
tci_out_label(s, args[5]);
|
|
break;
|
|
case INDEX_op_mulu2_i32:
|
|
tcg_out_r(s, args[0]);
|
|
tcg_out_r(s, args[1]);
|
|
tcg_out_r(s, args[2]);
|
|
tcg_out_r(s, args[3]);
|
|
break;
|
|
#endif
|
|
case INDEX_op_brcond_i32:
|
|
tcg_out_r(s, args[0]);
|
|
tcg_out_ri32(s, const_args[1], args[1]);
|
|
tcg_out8(s, args[2]); /* condition */
|
|
tci_out_label(s, args[3]);
|
|
break;
|
|
case INDEX_op_qemu_ld8u:
|
|
case INDEX_op_qemu_ld8s:
|
|
case INDEX_op_qemu_ld16u:
|
|
case INDEX_op_qemu_ld16s:
|
|
case INDEX_op_qemu_ld32:
|
|
#if TCG_TARGET_REG_BITS == 64
|
|
case INDEX_op_qemu_ld32s:
|
|
case INDEX_op_qemu_ld32u:
|
|
#endif
|
|
tcg_out_r(s, *args++);
|
|
tcg_out_r(s, *args++);
|
|
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
|
|
tcg_out_r(s, *args++);
|
|
#endif
|
|
#ifdef CONFIG_SOFTMMU
|
|
tcg_out_i(s, *args);
|
|
#endif
|
|
break;
|
|
case INDEX_op_qemu_ld64:
|
|
tcg_out_r(s, *args++);
|
|
#if TCG_TARGET_REG_BITS == 32
|
|
tcg_out_r(s, *args++);
|
|
#endif
|
|
tcg_out_r(s, *args++);
|
|
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
|
|
tcg_out_r(s, *args++);
|
|
#endif
|
|
#ifdef CONFIG_SOFTMMU
|
|
tcg_out_i(s, *args);
|
|
#endif
|
|
break;
|
|
case INDEX_op_qemu_st8:
|
|
case INDEX_op_qemu_st16:
|
|
case INDEX_op_qemu_st32:
|
|
tcg_out_r(s, *args++);
|
|
tcg_out_r(s, *args++);
|
|
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
|
|
tcg_out_r(s, *args++);
|
|
#endif
|
|
#ifdef CONFIG_SOFTMMU
|
|
tcg_out_i(s, *args);
|
|
#endif
|
|
break;
|
|
case INDEX_op_qemu_st64:
|
|
tcg_out_r(s, *args++);
|
|
#if TCG_TARGET_REG_BITS == 32
|
|
tcg_out_r(s, *args++);
|
|
#endif
|
|
tcg_out_r(s, *args++);
|
|
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
|
|
tcg_out_r(s, *args++);
|
|
#endif
|
|
#ifdef CONFIG_SOFTMMU
|
|
tcg_out_i(s, *args);
|
|
#endif
|
|
break;
|
|
case INDEX_op_end:
|
|
TODO();
|
|
break;
|
|
default:
|
|
fprintf(stderr, "Missing: %s\n", tcg_op_defs[opc].name);
|
|
tcg_abort();
|
|
}
|
|
old_code_ptr[1] = s->code_ptr - old_code_ptr;
|
|
}
|
|
|
|
static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
|
|
intptr_t arg2)
|
|
{
|
|
uint8_t *old_code_ptr = s->code_ptr;
|
|
if (type == TCG_TYPE_I32) {
|
|
tcg_out_op_t(s, INDEX_op_st_i32);
|
|
tcg_out_r(s, arg);
|
|
tcg_out_r(s, arg1);
|
|
tcg_out32(s, arg2);
|
|
} else {
|
|
assert(type == TCG_TYPE_I64);
|
|
#if TCG_TARGET_REG_BITS == 64
|
|
tcg_out_op_t(s, INDEX_op_st_i64);
|
|
tcg_out_r(s, arg);
|
|
tcg_out_r(s, arg1);
|
|
tcg_out32(s, arg2);
|
|
#else
|
|
TODO();
|
|
#endif
|
|
}
|
|
old_code_ptr[1] = s->code_ptr - old_code_ptr;
|
|
}
|
|
|
|
/* Test if a constant matches the constraint. */
|
|
static int tcg_target_const_match(tcg_target_long val, TCGType type,
|
|
const TCGArgConstraint *arg_ct)
|
|
{
|
|
/* No need to return 0 or 1, 0 or != 0 is good enough. */
|
|
return arg_ct->ct & TCG_CT_CONST;
|
|
}
|
|
|
|
static void tcg_target_init(TCGContext *s)
|
|
{
|
|
#if defined(CONFIG_DEBUG_TCG_INTERPRETER)
|
|
const char *envval = getenv("DEBUG_TCG");
|
|
if (envval) {
|
|
qemu_set_log(strtol(envval, NULL, 0));
|
|
}
|
|
#endif
|
|
|
|
/* The current code uses uint8_t for tcg operations. */
|
|
assert(ARRAY_SIZE(tcg_op_defs) <= UINT8_MAX);
|
|
|
|
/* Registers available for 32 bit operations. */
|
|
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0,
|
|
BIT(TCG_TARGET_NB_REGS) - 1);
|
|
/* Registers available for 64 bit operations. */
|
|
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0,
|
|
BIT(TCG_TARGET_NB_REGS) - 1);
|
|
/* TODO: Which registers should be set here? */
|
|
tcg_regset_set32(tcg_target_call_clobber_regs, 0,
|
|
BIT(TCG_TARGET_NB_REGS) - 1);
|
|
|
|
tcg_regset_clear(s->reserved_regs);
|
|
tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
|
|
tcg_add_target_add_op_defs(tcg_target_op_defs);
|
|
|
|
/* We use negative offsets from "sp" so that we can distinguish
|
|
stores that might pretend to be call arguments. */
|
|
tcg_set_frame(s, TCG_REG_CALL_STACK,
|
|
-CPU_TEMP_BUF_NLONGS * sizeof(long),
|
|
CPU_TEMP_BUF_NLONGS * sizeof(long));
|
|
}
|
|
|
|
/* Generate global QEMU prologue and epilogue code. */
|
|
static inline void tcg_target_qemu_prologue(TCGContext *s)
|
|
{
|
|
}
|