847 lines
23 KiB
C
847 lines
23 KiB
C
/*
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* s390 PCI instructions
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*
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* Copyright 2014 IBM Corp.
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* Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
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* Hong Bo Li <lihbbj@cn.ibm.com>
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* Yi Min Zhao <zyimin@cn.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or (at
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* your option) any later version. See the COPYING file in the top-level
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* directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "s390-pci-inst.h"
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#include "s390-pci-bus.h"
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#include <exec/memory-internal.h>
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#include <qemu/error-report.h>
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/* #define DEBUG_S390PCI_INST */
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#ifdef DEBUG_S390PCI_INST
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#define DPRINTF(fmt, ...) \
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do { fprintf(stderr, "s390pci-inst: " fmt, ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...) \
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do { } while (0)
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#endif
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static void s390_set_status_code(CPUS390XState *env,
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uint8_t r, uint64_t status_code)
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{
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env->regs[r] &= ~0xff000000ULL;
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env->regs[r] |= (status_code & 0xff) << 24;
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}
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static int list_pci(ClpReqRspListPci *rrb, uint8_t *cc)
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{
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S390PCIBusDevice *pbdev;
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uint32_t res_code, initial_l2, g_l2, finish;
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int rc, idx;
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uint64_t resume_token;
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rc = 0;
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if (lduw_p(&rrb->request.hdr.len) != 32) {
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res_code = CLP_RC_LEN;
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rc = -EINVAL;
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goto out;
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}
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if ((ldl_p(&rrb->request.fmt) & CLP_MASK_FMT) != 0) {
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res_code = CLP_RC_FMT;
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rc = -EINVAL;
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goto out;
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}
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if ((ldl_p(&rrb->request.fmt) & ~CLP_MASK_FMT) != 0 ||
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ldq_p(&rrb->request.reserved1) != 0 ||
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ldq_p(&rrb->request.reserved2) != 0) {
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res_code = CLP_RC_RESNOT0;
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rc = -EINVAL;
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goto out;
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}
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resume_token = ldq_p(&rrb->request.resume_token);
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if (resume_token) {
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pbdev = s390_pci_find_dev_by_idx(resume_token);
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if (!pbdev) {
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res_code = CLP_RC_LISTPCI_BADRT;
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rc = -EINVAL;
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goto out;
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}
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}
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if (lduw_p(&rrb->response.hdr.len) < 48) {
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res_code = CLP_RC_8K;
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rc = -EINVAL;
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goto out;
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}
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initial_l2 = lduw_p(&rrb->response.hdr.len);
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if ((initial_l2 - LIST_PCI_HDR_LEN) % sizeof(ClpFhListEntry)
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!= 0) {
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res_code = CLP_RC_LEN;
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rc = -EINVAL;
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*cc = 3;
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goto out;
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}
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stl_p(&rrb->response.fmt, 0);
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stq_p(&rrb->response.reserved1, 0);
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stq_p(&rrb->response.reserved2, 0);
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stl_p(&rrb->response.mdd, FH_VIRT);
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stw_p(&rrb->response.max_fn, PCI_MAX_FUNCTIONS);
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rrb->response.entry_size = sizeof(ClpFhListEntry);
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finish = 0;
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idx = resume_token;
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g_l2 = LIST_PCI_HDR_LEN;
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do {
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pbdev = s390_pci_find_dev_by_idx(idx);
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if (!pbdev) {
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finish = 1;
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break;
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}
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stw_p(&rrb->response.fh_list[idx - resume_token].device_id,
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pci_get_word(pbdev->pdev->config + PCI_DEVICE_ID));
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stw_p(&rrb->response.fh_list[idx - resume_token].vendor_id,
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pci_get_word(pbdev->pdev->config + PCI_VENDOR_ID));
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stl_p(&rrb->response.fh_list[idx - resume_token].config,
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pbdev->configured << 31);
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stl_p(&rrb->response.fh_list[idx - resume_token].fid, pbdev->fid);
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stl_p(&rrb->response.fh_list[idx - resume_token].fh, pbdev->fh);
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g_l2 += sizeof(ClpFhListEntry);
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/* Add endian check for DPRINTF? */
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DPRINTF("g_l2 %d vendor id 0x%x device id 0x%x fid 0x%x fh 0x%x\n",
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g_l2,
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lduw_p(&rrb->response.fh_list[idx - resume_token].vendor_id),
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lduw_p(&rrb->response.fh_list[idx - resume_token].device_id),
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ldl_p(&rrb->response.fh_list[idx - resume_token].fid),
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ldl_p(&rrb->response.fh_list[idx - resume_token].fh));
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idx++;
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} while (g_l2 < initial_l2);
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if (finish == 1) {
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resume_token = 0;
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} else {
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resume_token = idx;
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}
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stq_p(&rrb->response.resume_token, resume_token);
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stw_p(&rrb->response.hdr.len, g_l2);
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stw_p(&rrb->response.hdr.rsp, CLP_RC_OK);
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out:
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if (rc) {
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DPRINTF("list pci failed rc 0x%x\n", rc);
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stw_p(&rrb->response.hdr.rsp, res_code);
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}
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return rc;
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}
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int clp_service_call(S390CPU *cpu, uint8_t r2)
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{
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ClpReqHdr *reqh;
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ClpRspHdr *resh;
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S390PCIBusDevice *pbdev;
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uint32_t req_len;
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uint32_t res_len;
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uint8_t buffer[4096 * 2];
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uint8_t cc = 0;
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CPUS390XState *env = &cpu->env;
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int i;
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cpu_synchronize_state(CPU(cpu));
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if (env->psw.mask & PSW_MASK_PSTATE) {
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program_interrupt(env, PGM_PRIVILEGED, 4);
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return 0;
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}
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if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, sizeof(*reqh))) {
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return 0;
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}
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reqh = (ClpReqHdr *)buffer;
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req_len = lduw_p(&reqh->len);
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if (req_len < 16 || req_len > 8184 || (req_len % 8 != 0)) {
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program_interrupt(env, PGM_OPERAND, 4);
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return 0;
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}
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if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer,
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req_len + sizeof(*resh))) {
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return 0;
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}
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resh = (ClpRspHdr *)(buffer + req_len);
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res_len = lduw_p(&resh->len);
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if (res_len < 8 || res_len > 8176 || (res_len % 8 != 0)) {
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program_interrupt(env, PGM_OPERAND, 4);
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return 0;
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}
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if ((req_len + res_len) > 8192) {
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program_interrupt(env, PGM_OPERAND, 4);
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return 0;
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}
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if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer,
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req_len + res_len)) {
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return 0;
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}
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if (req_len != 32) {
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stw_p(&resh->rsp, CLP_RC_LEN);
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goto out;
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}
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switch (lduw_p(&reqh->cmd)) {
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case CLP_LIST_PCI: {
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ClpReqRspListPci *rrb = (ClpReqRspListPci *)buffer;
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list_pci(rrb, &cc);
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break;
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}
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case CLP_SET_PCI_FN: {
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ClpReqSetPci *reqsetpci = (ClpReqSetPci *)reqh;
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ClpRspSetPci *ressetpci = (ClpRspSetPci *)resh;
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pbdev = s390_pci_find_dev_by_fh(ldl_p(&reqsetpci->fh));
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if (!pbdev) {
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stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FH);
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goto out;
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}
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switch (reqsetpci->oc) {
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case CLP_SET_ENABLE_PCI_FN:
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pbdev->fh = pbdev->fh | FH_ENABLED;
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stl_p(&ressetpci->fh, pbdev->fh);
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stw_p(&ressetpci->hdr.rsp, CLP_RC_OK);
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break;
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case CLP_SET_DISABLE_PCI_FN:
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pbdev->fh = pbdev->fh & ~FH_ENABLED;
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pbdev->error_state = false;
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pbdev->lgstg_blocked = false;
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stl_p(&ressetpci->fh, pbdev->fh);
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stw_p(&ressetpci->hdr.rsp, CLP_RC_OK);
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break;
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default:
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DPRINTF("unknown set pci command\n");
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stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
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break;
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}
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break;
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}
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case CLP_QUERY_PCI_FN: {
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ClpReqQueryPci *reqquery = (ClpReqQueryPci *)reqh;
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ClpRspQueryPci *resquery = (ClpRspQueryPci *)resh;
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pbdev = s390_pci_find_dev_by_fh(ldl_p(&reqquery->fh));
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if (!pbdev) {
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DPRINTF("query pci no pci dev\n");
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stw_p(&resquery->hdr.rsp, CLP_RC_SETPCIFN_FH);
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goto out;
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}
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for (i = 0; i < PCI_BAR_COUNT; i++) {
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uint32_t data = pci_get_long(pbdev->pdev->config +
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PCI_BASE_ADDRESS_0 + (i * 4));
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stl_p(&resquery->bar[i], data);
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resquery->bar_size[i] = pbdev->pdev->io_regions[i].size ?
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ctz64(pbdev->pdev->io_regions[i].size) : 0;
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DPRINTF("bar %d addr 0x%x size 0x%" PRIx64 "barsize 0x%x\n", i,
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ldl_p(&resquery->bar[i]),
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pbdev->pdev->io_regions[i].size,
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resquery->bar_size[i]);
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}
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stq_p(&resquery->sdma, ZPCI_SDMA_ADDR);
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stq_p(&resquery->edma, ZPCI_EDMA_ADDR);
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stw_p(&resquery->pchid, 0);
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stw_p(&resquery->ug, 1);
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stl_p(&resquery->uid, pbdev->fid);
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stw_p(&resquery->hdr.rsp, CLP_RC_OK);
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break;
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}
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case CLP_QUERY_PCI_FNGRP: {
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ClpRspQueryPciGrp *resgrp = (ClpRspQueryPciGrp *)resh;
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resgrp->fr = 1;
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stq_p(&resgrp->dasm, 0);
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stq_p(&resgrp->msia, ZPCI_MSI_ADDR);
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stw_p(&resgrp->mui, 0);
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stw_p(&resgrp->i, 128);
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resgrp->version = 0;
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stw_p(&resgrp->hdr.rsp, CLP_RC_OK);
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break;
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}
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default:
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DPRINTF("unknown clp command\n");
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stw_p(&resh->rsp, CLP_RC_CMD);
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break;
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}
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out:
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if (s390_cpu_virt_mem_write(cpu, env->regs[r2], r2, buffer,
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req_len + res_len)) {
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return 0;
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}
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setcc(cpu, cc);
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return 0;
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}
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int pcilg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2)
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{
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CPUS390XState *env = &cpu->env;
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S390PCIBusDevice *pbdev;
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uint64_t offset;
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uint64_t data;
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uint8_t len;
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uint32_t fh;
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uint8_t pcias;
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cpu_synchronize_state(CPU(cpu));
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if (env->psw.mask & PSW_MASK_PSTATE) {
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program_interrupt(env, PGM_PRIVILEGED, 4);
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return 0;
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}
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if (r2 & 0x1) {
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program_interrupt(env, PGM_SPECIFICATION, 4);
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return 0;
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}
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fh = env->regs[r2] >> 32;
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pcias = (env->regs[r2] >> 16) & 0xf;
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len = env->regs[r2] & 0xf;
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offset = env->regs[r2 + 1];
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pbdev = s390_pci_find_dev_by_fh(fh);
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if (!pbdev || !(pbdev->fh & FH_ENABLED)) {
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DPRINTF("pcilg no pci dev\n");
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setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
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return 0;
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}
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if (pbdev->lgstg_blocked) {
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setcc(cpu, ZPCI_PCI_LS_ERR);
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s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED);
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return 0;
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}
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if (pcias < 6) {
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if ((8 - (offset & 0x7)) < len) {
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program_interrupt(env, PGM_OPERAND, 4);
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return 0;
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}
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MemoryRegion *mr = pbdev->pdev->io_regions[pcias].memory;
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memory_region_dispatch_read(mr, offset, &data, len,
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MEMTXATTRS_UNSPECIFIED);
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} else if (pcias == 15) {
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if ((4 - (offset & 0x3)) < len) {
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program_interrupt(env, PGM_OPERAND, 4);
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return 0;
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}
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data = pci_host_config_read_common(
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pbdev->pdev, offset, pci_config_size(pbdev->pdev), len);
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switch (len) {
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case 1:
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break;
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case 2:
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data = bswap16(data);
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break;
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case 4:
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data = bswap32(data);
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break;
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case 8:
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data = bswap64(data);
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break;
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default:
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program_interrupt(env, PGM_OPERAND, 4);
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return 0;
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}
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} else {
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DPRINTF("invalid space\n");
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setcc(cpu, ZPCI_PCI_LS_ERR);
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s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS);
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return 0;
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}
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env->regs[r1] = data;
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setcc(cpu, ZPCI_PCI_LS_OK);
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return 0;
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}
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static void update_msix_table_msg_data(S390PCIBusDevice *pbdev, uint64_t offset,
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uint64_t *data, uint8_t len)
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{
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uint32_t val;
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uint8_t *msg_data;
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if (offset % PCI_MSIX_ENTRY_SIZE != 8) {
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return;
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}
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if (len != 4) {
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DPRINTF("access msix table msg data but len is %d\n", len);
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return;
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}
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msg_data = (uint8_t *)data - offset % PCI_MSIX_ENTRY_SIZE +
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PCI_MSIX_ENTRY_VECTOR_CTRL;
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val = pci_get_long(msg_data) | (pbdev->fid << ZPCI_MSI_VEC_BITS);
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pci_set_long(msg_data, val);
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DPRINTF("update msix msg_data to 0x%" PRIx64 "\n", *data);
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}
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static int trap_msix(S390PCIBusDevice *pbdev, uint64_t offset, uint8_t pcias)
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{
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if (pbdev->msix.available && pbdev->msix.table_bar == pcias &&
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offset >= pbdev->msix.table_offset &&
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offset <= pbdev->msix.table_offset +
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(pbdev->msix.entries - 1) * PCI_MSIX_ENTRY_SIZE) {
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return 1;
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} else {
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return 0;
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}
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}
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int pcistg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2)
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{
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CPUS390XState *env = &cpu->env;
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uint64_t offset, data;
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S390PCIBusDevice *pbdev;
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uint8_t len;
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uint32_t fh;
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uint8_t pcias;
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cpu_synchronize_state(CPU(cpu));
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if (env->psw.mask & PSW_MASK_PSTATE) {
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program_interrupt(env, PGM_PRIVILEGED, 4);
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return 0;
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}
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if (r2 & 0x1) {
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program_interrupt(env, PGM_SPECIFICATION, 4);
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return 0;
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}
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fh = env->regs[r2] >> 32;
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pcias = (env->regs[r2] >> 16) & 0xf;
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len = env->regs[r2] & 0xf;
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offset = env->regs[r2 + 1];
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pbdev = s390_pci_find_dev_by_fh(fh);
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if (!pbdev || !(pbdev->fh & FH_ENABLED)) {
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DPRINTF("pcistg no pci dev\n");
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setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
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return 0;
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}
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if (pbdev->lgstg_blocked) {
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setcc(cpu, ZPCI_PCI_LS_ERR);
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s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED);
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return 0;
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}
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data = env->regs[r1];
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if (pcias < 6) {
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if ((8 - (offset & 0x7)) < len) {
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program_interrupt(env, PGM_OPERAND, 4);
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return 0;
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}
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MemoryRegion *mr;
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if (trap_msix(pbdev, offset, pcias)) {
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offset = offset - pbdev->msix.table_offset;
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mr = &pbdev->pdev->msix_table_mmio;
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update_msix_table_msg_data(pbdev, offset, &data, len);
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} else {
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mr = pbdev->pdev->io_regions[pcias].memory;
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}
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memory_region_dispatch_write(mr, offset, data, len,
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MEMTXATTRS_UNSPECIFIED);
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} else if (pcias == 15) {
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if ((4 - (offset & 0x3)) < len) {
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program_interrupt(env, PGM_OPERAND, 4);
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return 0;
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}
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switch (len) {
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case 1:
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break;
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case 2:
|
|
data = bswap16(data);
|
|
break;
|
|
case 4:
|
|
data = bswap32(data);
|
|
break;
|
|
case 8:
|
|
data = bswap64(data);
|
|
break;
|
|
default:
|
|
program_interrupt(env, PGM_OPERAND, 4);
|
|
return 0;
|
|
}
|
|
|
|
pci_host_config_write_common(pbdev->pdev, offset,
|
|
pci_config_size(pbdev->pdev),
|
|
data, len);
|
|
} else {
|
|
DPRINTF("pcistg invalid space\n");
|
|
setcc(cpu, ZPCI_PCI_LS_ERR);
|
|
s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS);
|
|
return 0;
|
|
}
|
|
|
|
setcc(cpu, ZPCI_PCI_LS_OK);
|
|
return 0;
|
|
}
|
|
|
|
int rpcit_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2)
|
|
{
|
|
CPUS390XState *env = &cpu->env;
|
|
uint32_t fh;
|
|
S390PCIBusDevice *pbdev;
|
|
hwaddr start, end;
|
|
IOMMUTLBEntry entry;
|
|
MemoryRegion *mr;
|
|
|
|
cpu_synchronize_state(CPU(cpu));
|
|
|
|
if (env->psw.mask & PSW_MASK_PSTATE) {
|
|
program_interrupt(env, PGM_PRIVILEGED, 4);
|
|
goto out;
|
|
}
|
|
|
|
if (r2 & 0x1) {
|
|
program_interrupt(env, PGM_SPECIFICATION, 4);
|
|
goto out;
|
|
}
|
|
|
|
fh = env->regs[r1] >> 32;
|
|
start = env->regs[r2];
|
|
end = start + env->regs[r2 + 1];
|
|
|
|
pbdev = s390_pci_find_dev_by_fh(fh);
|
|
if (!pbdev || !(pbdev->fh & FH_ENABLED)) {
|
|
DPRINTF("rpcit no pci dev\n");
|
|
setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
|
|
goto out;
|
|
}
|
|
|
|
mr = &pbdev->iommu_mr;
|
|
while (start < end) {
|
|
entry = mr->iommu_ops->translate(mr, start, 0);
|
|
|
|
if (!entry.translated_addr) {
|
|
setcc(cpu, ZPCI_PCI_LS_ERR);
|
|
goto out;
|
|
}
|
|
|
|
memory_region_notify_iommu(mr, entry);
|
|
start += entry.addr_mask + 1;
|
|
}
|
|
|
|
setcc(cpu, ZPCI_PCI_LS_OK);
|
|
out:
|
|
return 0;
|
|
}
|
|
|
|
int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
|
|
uint8_t ar)
|
|
{
|
|
CPUS390XState *env = &cpu->env;
|
|
S390PCIBusDevice *pbdev;
|
|
MemoryRegion *mr;
|
|
int i;
|
|
uint32_t fh;
|
|
uint8_t pcias;
|
|
uint8_t len;
|
|
uint8_t buffer[128];
|
|
|
|
if (env->psw.mask & PSW_MASK_PSTATE) {
|
|
program_interrupt(env, PGM_PRIVILEGED, 6);
|
|
return 0;
|
|
}
|
|
|
|
fh = env->regs[r1] >> 32;
|
|
pcias = (env->regs[r1] >> 16) & 0xf;
|
|
len = env->regs[r1] & 0xff;
|
|
|
|
if (pcias > 5) {
|
|
DPRINTF("pcistb invalid space\n");
|
|
setcc(cpu, ZPCI_PCI_LS_ERR);
|
|
s390_set_status_code(env, r1, ZPCI_PCI_ST_INVAL_AS);
|
|
return 0;
|
|
}
|
|
|
|
switch (len) {
|
|
case 16:
|
|
case 32:
|
|
case 64:
|
|
case 128:
|
|
break;
|
|
default:
|
|
program_interrupt(env, PGM_SPECIFICATION, 6);
|
|
return 0;
|
|
}
|
|
|
|
pbdev = s390_pci_find_dev_by_fh(fh);
|
|
if (!pbdev || !(pbdev->fh & FH_ENABLED)) {
|
|
DPRINTF("pcistb no pci dev fh 0x%x\n", fh);
|
|
setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
|
|
return 0;
|
|
}
|
|
|
|
if (pbdev->lgstg_blocked) {
|
|
setcc(cpu, ZPCI_PCI_LS_ERR);
|
|
s390_set_status_code(env, r1, ZPCI_PCI_ST_BLOCKED);
|
|
return 0;
|
|
}
|
|
|
|
mr = pbdev->pdev->io_regions[pcias].memory;
|
|
if (!memory_region_access_valid(mr, env->regs[r3], len, true)) {
|
|
program_interrupt(env, PGM_ADDRESSING, 6);
|
|
return 0;
|
|
}
|
|
|
|
if (s390_cpu_virt_mem_read(cpu, gaddr, ar, buffer, len)) {
|
|
return 0;
|
|
}
|
|
|
|
for (i = 0; i < len / 8; i++) {
|
|
memory_region_dispatch_write(mr, env->regs[r3] + i * 8,
|
|
ldq_p(buffer + i * 8), 8,
|
|
MEMTXATTRS_UNSPECIFIED);
|
|
}
|
|
|
|
setcc(cpu, ZPCI_PCI_LS_OK);
|
|
return 0;
|
|
}
|
|
|
|
static int reg_irqs(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib)
|
|
{
|
|
int ret, len;
|
|
|
|
ret = css_register_io_adapter(S390_PCIPT_ADAPTER,
|
|
FIB_DATA_ISC(ldl_p(&fib.data)), true, false,
|
|
&pbdev->routes.adapter.adapter_id);
|
|
assert(ret == 0);
|
|
|
|
pbdev->summary_ind = get_indicator(ldq_p(&fib.aisb), sizeof(uint64_t));
|
|
len = BITS_TO_LONGS(FIB_DATA_NOI(ldl_p(&fib.data))) * sizeof(unsigned long);
|
|
pbdev->indicator = get_indicator(ldq_p(&fib.aibv), len);
|
|
|
|
map_indicator(&pbdev->routes.adapter, pbdev->summary_ind);
|
|
map_indicator(&pbdev->routes.adapter, pbdev->indicator);
|
|
|
|
pbdev->routes.adapter.summary_addr = ldq_p(&fib.aisb);
|
|
pbdev->routes.adapter.summary_offset = FIB_DATA_AISBO(ldl_p(&fib.data));
|
|
pbdev->routes.adapter.ind_addr = ldq_p(&fib.aibv);
|
|
pbdev->routes.adapter.ind_offset = FIB_DATA_AIBVO(ldl_p(&fib.data));
|
|
pbdev->isc = FIB_DATA_ISC(ldl_p(&fib.data));
|
|
pbdev->noi = FIB_DATA_NOI(ldl_p(&fib.data));
|
|
pbdev->sum = FIB_DATA_SUM(ldl_p(&fib.data));
|
|
|
|
DPRINTF("reg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id);
|
|
return 0;
|
|
}
|
|
|
|
static int dereg_irqs(S390PCIBusDevice *pbdev)
|
|
{
|
|
release_indicator(&pbdev->routes.adapter, pbdev->summary_ind);
|
|
release_indicator(&pbdev->routes.adapter, pbdev->indicator);
|
|
|
|
pbdev->summary_ind = NULL;
|
|
pbdev->indicator = NULL;
|
|
pbdev->routes.adapter.summary_addr = 0;
|
|
pbdev->routes.adapter.summary_offset = 0;
|
|
pbdev->routes.adapter.ind_addr = 0;
|
|
pbdev->routes.adapter.ind_offset = 0;
|
|
pbdev->isc = 0;
|
|
pbdev->noi = 0;
|
|
pbdev->sum = 0;
|
|
|
|
DPRINTF("dereg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id);
|
|
return 0;
|
|
}
|
|
|
|
static int reg_ioat(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib)
|
|
{
|
|
uint64_t pba = ldq_p(&fib.pba);
|
|
uint64_t pal = ldq_p(&fib.pal);
|
|
uint64_t g_iota = ldq_p(&fib.iota);
|
|
uint8_t dt = (g_iota >> 2) & 0x7;
|
|
uint8_t t = (g_iota >> 11) & 0x1;
|
|
|
|
if (pba > pal || pba < ZPCI_SDMA_ADDR || pal > ZPCI_EDMA_ADDR) {
|
|
program_interrupt(env, PGM_OPERAND, 6);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* currently we only support designation type 1 with translation */
|
|
if (!(dt == ZPCI_IOTA_RTTO && t)) {
|
|
error_report("unsupported ioat dt %d t %d", dt, t);
|
|
program_interrupt(env, PGM_OPERAND, 6);
|
|
return -EINVAL;
|
|
}
|
|
|
|
pbdev->pba = pba;
|
|
pbdev->pal = pal;
|
|
pbdev->g_iota = g_iota;
|
|
|
|
s390_pcihost_iommu_configure(pbdev, true);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void dereg_ioat(S390PCIBusDevice *pbdev)
|
|
{
|
|
pbdev->pba = 0;
|
|
pbdev->pal = 0;
|
|
pbdev->g_iota = 0;
|
|
|
|
s390_pcihost_iommu_configure(pbdev, false);
|
|
}
|
|
|
|
int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar)
|
|
{
|
|
CPUS390XState *env = &cpu->env;
|
|
uint8_t oc;
|
|
uint32_t fh;
|
|
ZpciFib fib;
|
|
S390PCIBusDevice *pbdev;
|
|
uint64_t cc = ZPCI_PCI_LS_OK;
|
|
|
|
if (env->psw.mask & PSW_MASK_PSTATE) {
|
|
program_interrupt(env, PGM_PRIVILEGED, 6);
|
|
return 0;
|
|
}
|
|
|
|
oc = env->regs[r1] & 0xff;
|
|
fh = env->regs[r1] >> 32;
|
|
|
|
if (fiba & 0x7) {
|
|
program_interrupt(env, PGM_SPECIFICATION, 6);
|
|
return 0;
|
|
}
|
|
|
|
pbdev = s390_pci_find_dev_by_fh(fh);
|
|
if (!pbdev || !(pbdev->fh & FH_ENABLED)) {
|
|
DPRINTF("mpcifc no pci dev fh 0x%x\n", fh);
|
|
setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
|
|
return 0;
|
|
}
|
|
|
|
if (s390_cpu_virt_mem_read(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) {
|
|
return 0;
|
|
}
|
|
|
|
switch (oc) {
|
|
case ZPCI_MOD_FC_REG_INT:
|
|
if (reg_irqs(env, pbdev, fib)) {
|
|
cc = ZPCI_PCI_LS_ERR;
|
|
}
|
|
break;
|
|
case ZPCI_MOD_FC_DEREG_INT:
|
|
dereg_irqs(pbdev);
|
|
break;
|
|
case ZPCI_MOD_FC_REG_IOAT:
|
|
if (reg_ioat(env, pbdev, fib)) {
|
|
cc = ZPCI_PCI_LS_ERR;
|
|
}
|
|
break;
|
|
case ZPCI_MOD_FC_DEREG_IOAT:
|
|
dereg_ioat(pbdev);
|
|
break;
|
|
case ZPCI_MOD_FC_REREG_IOAT:
|
|
dereg_ioat(pbdev);
|
|
if (reg_ioat(env, pbdev, fib)) {
|
|
cc = ZPCI_PCI_LS_ERR;
|
|
}
|
|
break;
|
|
case ZPCI_MOD_FC_RESET_ERROR:
|
|
pbdev->error_state = false;
|
|
pbdev->lgstg_blocked = false;
|
|
break;
|
|
case ZPCI_MOD_FC_RESET_BLOCK:
|
|
pbdev->lgstg_blocked = false;
|
|
break;
|
|
case ZPCI_MOD_FC_SET_MEASURE:
|
|
pbdev->fmb_addr = ldq_p(&fib.fmb_addr);
|
|
break;
|
|
default:
|
|
program_interrupt(&cpu->env, PGM_OPERAND, 6);
|
|
cc = ZPCI_PCI_LS_ERR;
|
|
}
|
|
|
|
setcc(cpu, cc);
|
|
return 0;
|
|
}
|
|
|
|
int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar)
|
|
{
|
|
CPUS390XState *env = &cpu->env;
|
|
uint32_t fh;
|
|
ZpciFib fib;
|
|
S390PCIBusDevice *pbdev;
|
|
uint32_t data;
|
|
uint64_t cc = ZPCI_PCI_LS_OK;
|
|
|
|
if (env->psw.mask & PSW_MASK_PSTATE) {
|
|
program_interrupt(env, PGM_PRIVILEGED, 6);
|
|
return 0;
|
|
}
|
|
|
|
fh = env->regs[r1] >> 32;
|
|
|
|
if (fiba & 0x7) {
|
|
program_interrupt(env, PGM_SPECIFICATION, 6);
|
|
return 0;
|
|
}
|
|
|
|
pbdev = s390_pci_find_dev_by_fh(fh);
|
|
if (!pbdev) {
|
|
setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
|
|
return 0;
|
|
}
|
|
|
|
memset(&fib, 0, sizeof(fib));
|
|
stq_p(&fib.pba, pbdev->pba);
|
|
stq_p(&fib.pal, pbdev->pal);
|
|
stq_p(&fib.iota, pbdev->g_iota);
|
|
stq_p(&fib.aibv, pbdev->routes.adapter.ind_addr);
|
|
stq_p(&fib.aisb, pbdev->routes.adapter.summary_addr);
|
|
stq_p(&fib.fmb_addr, pbdev->fmb_addr);
|
|
|
|
data = ((uint32_t)pbdev->isc << 28) | ((uint32_t)pbdev->noi << 16) |
|
|
((uint32_t)pbdev->routes.adapter.ind_offset << 8) |
|
|
((uint32_t)pbdev->sum << 7) | pbdev->routes.adapter.summary_offset;
|
|
stl_p(&fib.data, data);
|
|
|
|
if (pbdev->fh & FH_ENABLED) {
|
|
fib.fc |= 0x80;
|
|
}
|
|
|
|
if (pbdev->error_state) {
|
|
fib.fc |= 0x40;
|
|
}
|
|
|
|
if (pbdev->lgstg_blocked) {
|
|
fib.fc |= 0x20;
|
|
}
|
|
|
|
if (pbdev->g_iota) {
|
|
fib.fc |= 0x10;
|
|
}
|
|
|
|
if (s390_cpu_virt_mem_write(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) {
|
|
return 0;
|
|
}
|
|
|
|
setcc(cpu, cc);
|
|
return 0;
|
|
}
|