2f57db8a27
Since c2077e2c "pci: Adjust PCI config limit based on bus topology",
pci_adjust_config_limit() has been used in the config space read and write
paths to only permit access to extended config space on buses which permit
it. Specifically it prevents access on devices below a vanilla-PCI bus via
some combination of bridges, even if both the host bridge and the device
itself are PCI-E.
It accomplishes this with a somewhat complex call up the chain of bridges
to see if any of them prohibit extended config space access. This is
overly complex, since we can always know if the bus will support such
access at the point it is constructed.
This patch simplifies the test by using a flag in the PCIBus instance
indicating whether extended configuration space is accessible. It is
false for vanilla PCI buses. For PCI-E buses, it is true for root
buses and equal to the parent bus's's capability otherwise.
For the special case of sPAPR's paravirtualized PCI root bus, which
acts mostly like vanilla PCI, but does allow extended config space
access, we override the default value of the flag from the host bridge
code.
This should cause no behavioural change.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
Message-Id: <20190513061939.3464-4-david@gibson.dropbear.id.au>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
67 lines
1.7 KiB
C
67 lines
1.7 KiB
C
#ifndef QEMU_PCI_BUS_H
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#define QEMU_PCI_BUS_H
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#include "hw/pci/pci.h"
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/*
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* PCI Bus datastructures.
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*
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* Do not access the following members directly;
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* use accessor functions in pci.h
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*/
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typedef struct PCIBusClass {
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/*< private >*/
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BusClass parent_class;
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/*< public >*/
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int (*bus_num)(PCIBus *bus);
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uint16_t (*numa_node)(PCIBus *bus);
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} PCIBusClass;
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enum PCIBusFlags {
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/* This bus is the root of a PCI domain */
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PCI_BUS_IS_ROOT = 0x0001,
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/* PCIe extended configuration space is accessible on this bus */
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PCI_BUS_EXTENDED_CONFIG_SPACE = 0x0002,
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};
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struct PCIBus {
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BusState qbus;
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enum PCIBusFlags flags;
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PCIIOMMUFunc iommu_fn;
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void *iommu_opaque;
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uint8_t devfn_min;
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uint32_t slot_reserved_mask;
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pci_set_irq_fn set_irq;
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pci_map_irq_fn map_irq;
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pci_route_irq_fn route_intx_to_irq;
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void *irq_opaque;
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PCIDevice *devices[PCI_SLOT_MAX * PCI_FUNC_MAX];
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PCIDevice *parent_dev;
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MemoryRegion *address_space_mem;
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MemoryRegion *address_space_io;
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QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
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QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
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/* The bus IRQ state is the logical OR of the connected devices.
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Keep a count of the number of devices with raised IRQs. */
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int nirq;
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int *irq_count;
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Notifier machine_done;
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};
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static inline bool pci_bus_is_root(PCIBus *bus)
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{
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return !!(bus->flags & PCI_BUS_IS_ROOT);
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}
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static inline bool pci_bus_allows_extended_config_space(PCIBus *bus)
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{
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return !!(bus->flags & PCI_BUS_EXTENDED_CONFIG_SPACE);
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}
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#endif /* QEMU_PCI_BUS_H */
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