441 lines
15 KiB
C
441 lines
15 KiB
C
/*
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* ARM Aspeed I2C controller
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*
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* Copyright (C) 2016 IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "qemu/log.h"
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#include "hw/i2c/aspeed_i2c.h"
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/* I2C Global Register */
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#define I2C_CTRL_STATUS 0x00 /* Device Interrupt Status */
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#define I2C_CTRL_ASSIGN 0x08 /* Device Interrupt Target
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Assignment */
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/* I2C Device (Bus) Register */
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#define I2CD_FUN_CTRL_REG 0x00 /* I2CD Function Control */
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#define I2CD_BUFF_SEL_MASK (0x7 << 20)
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#define I2CD_BUFF_SEL(x) (x << 20)
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#define I2CD_M_SDA_LOCK_EN (0x1 << 16)
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#define I2CD_MULTI_MASTER_DIS (0x1 << 15)
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#define I2CD_M_SCL_DRIVE_EN (0x1 << 14)
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#define I2CD_MSB_STS (0x1 << 9)
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#define I2CD_SDA_DRIVE_1T_EN (0x1 << 8)
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#define I2CD_M_SDA_DRIVE_1T_EN (0x1 << 7)
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#define I2CD_M_HIGH_SPEED_EN (0x1 << 6)
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#define I2CD_DEF_ADDR_EN (0x1 << 5)
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#define I2CD_DEF_ALERT_EN (0x1 << 4)
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#define I2CD_DEF_ARP_EN (0x1 << 3)
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#define I2CD_DEF_GCALL_EN (0x1 << 2)
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#define I2CD_SLAVE_EN (0x1 << 1)
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#define I2CD_MASTER_EN (0x1)
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#define I2CD_AC_TIMING_REG1 0x04 /* Clock and AC Timing Control #1 */
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#define I2CD_AC_TIMING_REG2 0x08 /* Clock and AC Timing Control #1 */
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#define I2CD_INTR_CTRL_REG 0x0c /* I2CD Interrupt Control */
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#define I2CD_INTR_STS_REG 0x10 /* I2CD Interrupt Status */
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#define I2CD_INTR_SDA_DL_TIMEOUT (0x1 << 14)
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#define I2CD_INTR_BUS_RECOVER_DONE (0x1 << 13)
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#define I2CD_INTR_SMBUS_ALERT (0x1 << 12) /* Bus [0-3] only */
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#define I2CD_INTR_SMBUS_ARP_ADDR (0x1 << 11) /* Removed */
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#define I2CD_INTR_SMBUS_DEV_ALERT_ADDR (0x1 << 10) /* Removed */
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#define I2CD_INTR_SMBUS_DEF_ADDR (0x1 << 9) /* Removed */
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#define I2CD_INTR_GCALL_ADDR (0x1 << 8) /* Removed */
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#define I2CD_INTR_SLAVE_MATCH (0x1 << 7) /* use RX_DONE */
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#define I2CD_INTR_SCL_TIMEOUT (0x1 << 6)
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#define I2CD_INTR_ABNORMAL (0x1 << 5)
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#define I2CD_INTR_NORMAL_STOP (0x1 << 4)
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#define I2CD_INTR_ARBIT_LOSS (0x1 << 3)
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#define I2CD_INTR_RX_DONE (0x1 << 2)
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#define I2CD_INTR_TX_NAK (0x1 << 1)
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#define I2CD_INTR_TX_ACK (0x1 << 0)
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#define I2CD_CMD_REG 0x14 /* I2CD Command/Status */
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#define I2CD_SDA_OE (0x1 << 28)
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#define I2CD_SDA_O (0x1 << 27)
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#define I2CD_SCL_OE (0x1 << 26)
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#define I2CD_SCL_O (0x1 << 25)
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#define I2CD_TX_TIMING (0x1 << 24)
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#define I2CD_TX_STATUS (0x1 << 23)
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#define I2CD_TX_STATE_SHIFT 19 /* Tx State Machine */
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#define I2CD_TX_STATE_MASK 0xf
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#define I2CD_IDLE 0x0
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#define I2CD_MACTIVE 0x8
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#define I2CD_MSTART 0x9
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#define I2CD_MSTARTR 0xa
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#define I2CD_MSTOP 0xb
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#define I2CD_MTXD 0xc
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#define I2CD_MRXACK 0xd
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#define I2CD_MRXD 0xe
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#define I2CD_MTXACK 0xf
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#define I2CD_SWAIT 0x1
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#define I2CD_SRXD 0x4
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#define I2CD_STXACK 0x5
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#define I2CD_STXD 0x6
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#define I2CD_SRXACK 0x7
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#define I2CD_RECOVER 0x3
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#define I2CD_SCL_LINE_STS (0x1 << 18)
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#define I2CD_SDA_LINE_STS (0x1 << 17)
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#define I2CD_BUS_BUSY_STS (0x1 << 16)
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#define I2CD_SDA_OE_OUT_DIR (0x1 << 15)
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#define I2CD_SDA_O_OUT_DIR (0x1 << 14)
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#define I2CD_SCL_OE_OUT_DIR (0x1 << 13)
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#define I2CD_SCL_O_OUT_DIR (0x1 << 12)
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#define I2CD_BUS_RECOVER_CMD_EN (0x1 << 11)
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#define I2CD_S_ALT_EN (0x1 << 10)
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#define I2CD_RX_DMA_ENABLE (0x1 << 9)
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#define I2CD_TX_DMA_ENABLE (0x1 << 8)
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/* Command Bit */
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#define I2CD_M_STOP_CMD (0x1 << 5)
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#define I2CD_M_S_RX_CMD_LAST (0x1 << 4)
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#define I2CD_M_RX_CMD (0x1 << 3)
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#define I2CD_S_TX_CMD (0x1 << 2)
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#define I2CD_M_TX_CMD (0x1 << 1)
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#define I2CD_M_START_CMD (0x1)
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#define I2CD_DEV_ADDR_REG 0x18 /* Slave Device Address */
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#define I2CD_BUF_CTRL_REG 0x1c /* Pool Buffer Control */
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#define I2CD_BYTE_BUF_REG 0x20 /* Transmit/Receive Byte Buffer */
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#define I2CD_BYTE_BUF_TX_SHIFT 0
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#define I2CD_BYTE_BUF_TX_MASK 0xff
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#define I2CD_BYTE_BUF_RX_SHIFT 8
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#define I2CD_BYTE_BUF_RX_MASK 0xff
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static inline bool aspeed_i2c_bus_is_master(AspeedI2CBus *bus)
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{
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return bus->ctrl & I2CD_MASTER_EN;
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}
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static inline bool aspeed_i2c_bus_is_enabled(AspeedI2CBus *bus)
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{
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return bus->ctrl & (I2CD_MASTER_EN | I2CD_SLAVE_EN);
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}
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static inline void aspeed_i2c_bus_raise_interrupt(AspeedI2CBus *bus)
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{
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bus->intr_status &= bus->intr_ctrl;
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if (bus->intr_status) {
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bus->controller->intr_status |= 1 << bus->id;
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qemu_irq_raise(bus->controller->irq);
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}
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}
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static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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AspeedI2CBus *bus = opaque;
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switch (offset) {
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case I2CD_FUN_CTRL_REG:
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return bus->ctrl;
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case I2CD_AC_TIMING_REG1:
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return bus->timing[0];
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case I2CD_AC_TIMING_REG2:
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return bus->timing[1];
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case I2CD_INTR_CTRL_REG:
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return bus->intr_ctrl;
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case I2CD_INTR_STS_REG:
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return bus->intr_status;
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case I2CD_BYTE_BUF_REG:
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return bus->buf;
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case I2CD_CMD_REG:
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return bus->cmd | (i2c_bus_busy(bus->bus) << 16);
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset);
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return -1;
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}
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}
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static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
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{
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bus->cmd |= value & 0xFFFF;
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bus->intr_status = 0;
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if (bus->cmd & I2CD_M_START_CMD) {
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if (i2c_start_transfer(bus->bus, extract32(bus->buf, 1, 7),
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extract32(bus->buf, 0, 1))) {
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bus->intr_status |= I2CD_INTR_TX_NAK;
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} else {
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bus->intr_status |= I2CD_INTR_TX_ACK;
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}
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} else if (bus->cmd & I2CD_M_TX_CMD) {
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if (i2c_send(bus->bus, bus->buf)) {
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bus->intr_status |= (I2CD_INTR_TX_NAK | I2CD_INTR_ABNORMAL);
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i2c_end_transfer(bus->bus);
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} else {
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bus->intr_status |= I2CD_INTR_TX_ACK;
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}
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} else if (bus->cmd & I2CD_M_RX_CMD) {
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int ret = i2c_recv(bus->bus);
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if (ret < 0) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: read failed\n", __func__);
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ret = 0xff;
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} else {
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bus->intr_status |= I2CD_INTR_RX_DONE;
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}
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bus->buf = (ret & I2CD_BYTE_BUF_RX_MASK) << I2CD_BYTE_BUF_RX_SHIFT;
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}
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if (bus->cmd & (I2CD_M_STOP_CMD | I2CD_M_S_RX_CMD_LAST)) {
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if (!i2c_bus_busy(bus->bus)) {
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bus->intr_status |= I2CD_INTR_ABNORMAL;
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} else {
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i2c_end_transfer(bus->bus);
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bus->intr_status |= I2CD_INTR_NORMAL_STOP;
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}
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}
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/* command is handled, reset it and check for interrupts */
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bus->cmd &= ~0xFFFF;
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aspeed_i2c_bus_raise_interrupt(bus);
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}
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static void aspeed_i2c_bus_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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AspeedI2CBus *bus = opaque;
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switch (offset) {
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case I2CD_FUN_CTRL_REG:
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if (value & I2CD_SLAVE_EN) {
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qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n",
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__func__);
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break;
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}
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bus->ctrl = value & 0x0071C3FF;
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break;
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case I2CD_AC_TIMING_REG1:
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bus->timing[0] = value & 0xFFFFF0F;
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break;
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case I2CD_AC_TIMING_REG2:
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bus->timing[1] = value & 0x7;
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break;
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case I2CD_INTR_CTRL_REG:
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bus->intr_ctrl = value & 0x7FFF;
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break;
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case I2CD_INTR_STS_REG:
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bus->intr_status &= ~(value & 0x7FFF);
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bus->controller->intr_status &= ~(1 << bus->id);
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qemu_irq_lower(bus->controller->irq);
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break;
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case I2CD_DEV_ADDR_REG:
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qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n",
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__func__);
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break;
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case I2CD_BYTE_BUF_REG:
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bus->buf = (value & I2CD_BYTE_BUF_TX_MASK) << I2CD_BYTE_BUF_TX_SHIFT;
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break;
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case I2CD_CMD_REG:
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if (!aspeed_i2c_bus_is_enabled(bus)) {
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break;
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}
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if (!aspeed_i2c_bus_is_master(bus)) {
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qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n",
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__func__);
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break;
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}
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aspeed_i2c_bus_handle_cmd(bus, value);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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}
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}
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static uint64_t aspeed_i2c_ctrl_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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AspeedI2CState *s = opaque;
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switch (offset) {
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case I2C_CTRL_STATUS:
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return s->intr_status;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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break;
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}
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return -1;
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}
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static void aspeed_i2c_ctrl_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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switch (offset) {
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case I2C_CTRL_STATUS:
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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break;
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}
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}
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static const MemoryRegionOps aspeed_i2c_bus_ops = {
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.read = aspeed_i2c_bus_read,
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.write = aspeed_i2c_bus_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static const MemoryRegionOps aspeed_i2c_ctrl_ops = {
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.read = aspeed_i2c_ctrl_read,
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.write = aspeed_i2c_ctrl_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static const VMStateDescription aspeed_i2c_bus_vmstate = {
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.name = TYPE_ASPEED_I2C,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(id, AspeedI2CBus),
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VMSTATE_UINT32(ctrl, AspeedI2CBus),
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VMSTATE_UINT32_ARRAY(timing, AspeedI2CBus, 2),
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VMSTATE_UINT32(intr_ctrl, AspeedI2CBus),
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VMSTATE_UINT32(intr_status, AspeedI2CBus),
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VMSTATE_UINT32(cmd, AspeedI2CBus),
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VMSTATE_UINT32(buf, AspeedI2CBus),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription aspeed_i2c_vmstate = {
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.name = TYPE_ASPEED_I2C,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(intr_status, AspeedI2CState),
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VMSTATE_STRUCT_ARRAY(busses, AspeedI2CState,
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ASPEED_I2C_NR_BUSSES, 1, aspeed_i2c_bus_vmstate,
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AspeedI2CBus),
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VMSTATE_END_OF_LIST()
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}
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};
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static void aspeed_i2c_reset(DeviceState *dev)
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{
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int i;
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AspeedI2CState *s = ASPEED_I2C(dev);
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s->intr_status = 0;
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for (i = 0; i < ASPEED_I2C_NR_BUSSES; i++) {
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s->busses[i].intr_ctrl = 0;
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s->busses[i].intr_status = 0;
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s->busses[i].cmd = 0;
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s->busses[i].buf = 0;
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i2c_end_transfer(s->busses[i].bus);
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}
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}
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/*
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* Address Definitions
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*
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* 0x000 ... 0x03F: Global Register
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* 0x040 ... 0x07F: Device 1
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* 0x080 ... 0x0BF: Device 2
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* 0x0C0 ... 0x0FF: Device 3
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* 0x100 ... 0x13F: Device 4
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* 0x140 ... 0x17F: Device 5
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* 0x180 ... 0x1BF: Device 6
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* 0x1C0 ... 0x1FF: Device 7
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* 0x200 ... 0x2FF: Buffer Pool (unused in linux driver)
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* 0x300 ... 0x33F: Device 8
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* 0x340 ... 0x37F: Device 9
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* 0x380 ... 0x3BF: Device 10
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* 0x3C0 ... 0x3FF: Device 11
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* 0x400 ... 0x43F: Device 12
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* 0x440 ... 0x47F: Device 13
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* 0x480 ... 0x4BF: Device 14
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* 0x800 ... 0xFFF: Buffer Pool (unused in linux driver)
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*/
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static void aspeed_i2c_realize(DeviceState *dev, Error **errp)
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{
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int i;
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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AspeedI2CState *s = ASPEED_I2C(dev);
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sysbus_init_irq(sbd, &s->irq);
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memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i2c_ctrl_ops, s,
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"aspeed.i2c", 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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for (i = 0; i < ASPEED_I2C_NR_BUSSES; i++) {
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char name[16];
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int offset = i < 7 ? 1 : 5;
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snprintf(name, sizeof(name), "aspeed.i2c.%d", i);
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s->busses[i].controller = s;
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s->busses[i].id = i;
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s->busses[i].bus = i2c_init_bus(dev, name);
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memory_region_init_io(&s->busses[i].mr, OBJECT(dev),
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&aspeed_i2c_bus_ops, &s->busses[i], name, 0x40);
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memory_region_add_subregion(&s->iomem, 0x40 * (i + offset),
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&s->busses[i].mr);
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}
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}
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static void aspeed_i2c_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &aspeed_i2c_vmstate;
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dc->reset = aspeed_i2c_reset;
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dc->realize = aspeed_i2c_realize;
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dc->desc = "Aspeed I2C Controller";
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}
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static const TypeInfo aspeed_i2c_info = {
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.name = TYPE_ASPEED_I2C,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(AspeedI2CState),
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.class_init = aspeed_i2c_class_init,
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};
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static void aspeed_i2c_register_types(void)
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{
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type_register_static(&aspeed_i2c_info);
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}
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type_init(aspeed_i2c_register_types)
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I2CBus *aspeed_i2c_get_bus(DeviceState *dev, int busnr)
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{
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AspeedI2CState *s = ASPEED_I2C(dev);
|
|
I2CBus *bus = NULL;
|
|
|
|
if (busnr >= 0 && busnr < ASPEED_I2C_NR_BUSSES) {
|
|
bus = s->busses[busnr].bus;
|
|
}
|
|
|
|
return bus;
|
|
}
|