qemu-e2k/include/hw/char
Clément Chigot f432962e72 hw/sparc/grlib: split out the headers for each peripherals
Split out the headers for each peripherals and move them in their
right hardware directory.

Update Copyright and add SPDX-License-Identifier at the same time.

Co-developed-by: Frederic Konrad <konrad.frederic@yahoo.fr>
Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240131085047.18458-2-chigot@adacore.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-15 16:58:46 +01:00
..
avr_usart.h include/: spelling fixes 2023-09-08 13:08:52 +03:00
bcm2835_aux.h
cadence_uart.h
cmsdk-apb-uart.h hw/char/cmsdk-apb-uart: Open-code cmsdk_apb_uart_create() 2023-02-27 13:27:05 +00:00
digic-uart.h
escc.h escc: emulate dip switch language layout settings on SUN keyboard 2023-06-28 10:54:25 +01:00
goldfish_tty.h
grlib_uart.h hw/sparc/grlib: split out the headers for each peripherals 2024-02-15 16:58:46 +01:00
ibex_uart.h include/hw: Do not include "hw/registerfields.h" in headers that don't need it 2023-02-14 09:02:42 +01:00
imx_serial.h hw/char/imx_serial: Implement receive FIFO and ageing timer 2024-01-26 11:34:21 +00:00
mchp_pfsoc_mmuart.h
nrf51_uart.h
parallel-isa.h hw/char/parallel-isa: Implement relocation and enabling/disabling for TYPE_ISA_PARALLEL 2024-02-14 06:09:32 -05:00
parallel.h hw/char/parallel: Move portio_list from ParallelState to ISAParallelState 2024-02-14 06:09:32 -05:00
pl011.h hw/char/pl011: Open-code pl011_luminary_create() 2023-02-27 13:27:05 +00:00
renesas_sci.h
riscv_htif.h hw/riscv: Add signature dump function for spike to run ACT tests 2023-05-05 10:49:50 +10:00
serial.h hw/char/serial-isa: Implement relocation and enabling/disabling for TYPE_ISA_SERIAL 2024-02-14 06:09:32 -05:00
shakti_uart.h
sifive_uart.h
stm32f2xx_usart.h hw/char/stm32f2xx_usart: Add more definitions for CR1 register 2023-11-02 13:36:45 +00:00
xilinx_uartlite.h hw/char/xilinx_uartlite: Open-code xilinx_uartlite_create() 2023-02-27 13:27:05 +00:00