Richard Henderson dfd1b81274 accel/tcg: Introduce translator_io_start ... New wrapper around gen_io_start which takes care of the USE_ICOUNT check, as well as marking the DisasContext to end the TB. Remove exec/gen-icount.h. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>		2023-06-05 12:04:29 -07:00
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trans_privileged.c.inc	accel/tcg: Introduce translator_io_start	2023-06-05 12:04:29 -07:00
trans_rva.c.inc	target/riscv: Ensure opcode is saved for all relevant instructions	2023-02-07 08:19:23 +10:00
trans_rvb.c.inc	target/riscv: Drop tcg_temp_free	2023-03-05 13:44:08 -08:00
trans_rvd.c.inc	target/riscv: add support for Zcd extension	2023-05-05 10:49:50 +10:00
trans_rvf.c.inc	target/riscv: Encode the FS and VS on a normal way for tb flags	2023-05-05 10:49:50 +10:00
trans_rvh.c.inc	target/riscv: Handle HLV, HSV via helpers	2023-05-05 10:49:50 +10:00
trans_rvi.c.inc	accel/tcg: Introduce translator_io_start	2023-06-05 12:04:29 -07:00
trans_rvk.c.inc	target/riscv: Drop tcg_temp_free	2023-03-05 13:44:08 -08:00
trans_rvm.c.inc	target/riscv: Drop tcg_temp_free	2023-03-05 13:44:08 -08:00
trans_rvv.c.inc	target/riscv: Add a tb flags field for vstart	2023-05-05 10:49:50 +10:00
trans_rvzawrs.c.inc	RISC-V: Add Zawrs ISA extension support	2023-01-06 10:42:55 +10:00
trans_rvzce.c.inc	target/riscv: remove cpu->cfg.ext_e	2023-05-05 10:49:50 +10:00
trans_rvzfh.c.inc	target/riscv: Avoid tcg_const_*	2023-03-05 13:46:13 -08:00
trans_rvzicbo.c.inc	target/riscv: implement Zicbom extension	2023-03-05 11:49:42 -08:00
trans_rvzicond.c.inc	target/riscv: refactor Zicond support	2023-05-05 10:49:50 +10:00
trans_svinval.c.inc	target/riscv: Ensure opcode is saved for all relevant instructions	2023-02-07 08:19:23 +10:00
trans_xthead.c.inc	target/riscv: Separate priv from mmu_idx	2023-05-05 10:49:50 +10:00
trans_xventanacondops.c.inc	target/riscv: redirect XVentanaCondOps to use the Zicond functions	2023-05-05 10:49:50 +10:00