Peter Maydell dfff1000fe target/arm: Implement Neoverse N2 CPU model ... Implement a model of the Neoverse N2 CPU. This is an Armv9.0-A processor very similar to the Cortex-A710. The differences are: * no FEAT_EVT * FEAT_DGH (data gathering hint) * FEAT_NV (not yet implemented in QEMU) * Statistical Profiling Extension (not implemented in QEMU) * 48 bit physical address range, not 40 * CTR_EL0.DIC = 1 (no explicit icache cleaning needed) * PMCR_EL0.N = 6 (always 6 PMU counters, not 20) Because it has 48-bit physical address support, we can use this CPU in the sbsa-ref board as well as the virt board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20230915185453.1871167-3-peter.maydell@linaro.org		2023-10-27 11:41:13 +01:00
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a32-uncond.decode
a32.decode
a64.decode	target/arm: Implement the CPY* instructions	2023-09-21 16:07:14 +01:00
arm_ldst.h	target/arm: Move translate-a32.h, arm_ldst.h, sve_ldst_internal.h to tcg/	2023-05-12 15:43:36 +01:00
cpu32.c	target/arm: Implement FEAT_HPMN0	2023-10-19 14:32:13 +01:00
cpu64.c	target/arm: Implement Neoverse N2 CPU model	2023-10-27 11:41:13 +01:00
crypto_helper.c	crypto: Create sm4_subword	2023-09-11 11:45:55 +10:00
helper-a64.c	target/arm: Implement the CPY* instructions	2023-09-21 16:07:14 +01:00
helper-a64.h	target/arm: Implement the CPY* instructions	2023-09-21 16:07:14 +01:00
helper-mve.h	target/arm: Move helper-{a64,mve,sme,sve}.h to tcg/	2023-05-12 15:43:37 +01:00
helper-sme.h	target/arm: Move helper-{a64,mve,sme,sve}.h to tcg/	2023-05-12 15:43:37 +01:00
helper-sve.h	target/arm: Move helper-{a64,mve,sme,sve}.h to tcg/	2023-05-12 15:43:37 +01:00
hflags.c	target/arm: Define new TB flag for ATA0	2023-09-21 16:07:14 +01:00
iwmmxt_helper.c
m_helper.c	arm: spelling fixes	2023-07-25 17:13:53 +03:00
m-nocp.decode
meson.build	target/arm/tcg: Don't build AArch64 decodetree files for qemu-system-arm	2023-07-31 11:41:21 +01:00
mte_helper.c	target/arm: Replace TARGET_PAGE_ENTRY_EXTRA	2023-10-03 08:01:02 -07:00
mve_helper.c	target/arm/tcg: Clean up local variable shadowing	2023-09-29 10:07:14 +02:00
mve.decode
neon_helper.c
neon-dp.decode
neon-ls.decode
neon-shared.decode
op_helper.c	target/arm: Implement FEAT_TIDCP1	2023-09-08 16:41:35 +01:00
pauth_helper.c	target/arm: Implement FEAT_FPAC and FEAT_FPACCOMBINE	2023-09-08 12:51:01 +01:00
psci.c
sme_helper.c	target/arm: Fix SME ST1Q	2023-08-22 17:31:13 +01:00
sme-fa64.decode
sme.decode
sve_helper.c	target/arm: Replace TARGET_PAGE_ENTRY_EXTRA	2023-10-03 08:01:02 -07:00
sve_ldst_internal.h	target/arm: Move translate-a32.h, arm_ldst.h, sve_ldst_internal.h to tcg/	2023-05-12 15:43:36 +01:00
sve.decode	target/arm: Demultiplex AESE and AESMC	2023-07-08 07:30:18 +01:00
t16.decode
t32.decode
tlb_helper.c	target/arm: Replace TARGET_PAGE_ENTRY_EXTRA	2023-10-03 08:01:02 -07:00
translate-a32.h	tcg: Rename cpu_env to tcg_env	2023-10-03 08:01:02 -07:00
translate-a64.c	target/arm: Use tcg_gen_ext_i64	2023-10-22 16:35:43 -07:00
translate-a64.h	tcg: Rename cpu_env to tcg_env	2023-10-03 08:01:02 -07:00
translate-m-nocp.c	tcg: Rename cpu_env to tcg_env	2023-10-03 08:01:02 -07:00
translate-mve.c	tcg: Rename cpu_env to tcg_env	2023-10-03 08:01:02 -07:00
translate-neon.c	tcg: Rename cpu_env to tcg_env	2023-10-03 08:01:02 -07:00
translate-sme.c	tcg: Rename cpu_env to tcg_env	2023-10-03 08:01:02 -07:00
translate-sve.c	tcg: Rename cpu_env to tcg_env	2023-10-03 08:01:02 -07:00
translate-vfp.c	tcg: Rename cpu_env to tcg_env	2023-10-03 08:01:02 -07:00
translate.c	target/arm: Permit T32 LDM with single register	2023-10-19 14:32:13 +01:00
translate.h	tcg: Rename cpu_env to tcg_env	2023-10-03 08:01:02 -07:00
vec_helper.c	target/arm: Use clmul_64	2023-09-15 13:57:00 +00:00
vec_internal.h	target/arm: Use clmul_16* routines	2023-09-15 13:57:00 +00:00
vfp-uncond.decode
vfp.decode