902 lines
27 KiB
C
902 lines
27 KiB
C
/*
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* Sparc CPU init helpers
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "qemu/error-report.h"
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#include "exec/exec-all.h"
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//#define DEBUG_FEATURES
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static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model);
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/* CPUClass::reset() */
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static void sparc_cpu_reset(CPUState *s)
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{
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SPARCCPU *cpu = SPARC_CPU(s);
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SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(cpu);
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CPUSPARCState *env = &cpu->env;
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scc->parent_reset(s);
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memset(env, 0, offsetof(CPUSPARCState, end_reset_fields));
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env->cwp = 0;
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#ifndef TARGET_SPARC64
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env->wim = 1;
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#endif
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env->regwptr = env->regbase + (env->cwp * 16);
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CC_OP = CC_OP_FLAGS;
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#if defined(CONFIG_USER_ONLY)
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#ifdef TARGET_SPARC64
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env->cleanwin = env->nwindows - 2;
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env->cansave = env->nwindows - 2;
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env->pstate = PS_RMO | PS_PEF | PS_IE;
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env->asi = 0x82; /* Primary no-fault */
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#endif
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#else
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#if !defined(TARGET_SPARC64)
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env->psret = 0;
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env->psrs = 1;
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env->psrps = 1;
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#endif
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#ifdef TARGET_SPARC64
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env->pstate = PS_PRIV | PS_RED | PS_PEF;
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if (!cpu_has_hypervisor(env)) {
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env->pstate |= PS_AG;
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}
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env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0;
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env->tl = env->maxtl;
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env->gl = 2;
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cpu_tsptr(env)->tt = TT_POWER_ON_RESET;
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env->lsu = 0;
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#else
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env->mmuregs[0] &= ~(MMU_E | MMU_NF);
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env->mmuregs[0] |= env->def->mmu_bm;
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#endif
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env->pc = 0;
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env->npc = env->pc + 4;
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#endif
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env->cache_control = 0;
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}
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static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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SPARCCPU *cpu = SPARC_CPU(cs);
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CPUSPARCState *env = &cpu->env;
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if (cpu_interrupts_enabled(env) && env->interrupt_index > 0) {
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int pil = env->interrupt_index & 0xf;
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int type = env->interrupt_index & 0xf0;
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if (type != TT_EXTINT || cpu_pil_allowed(env, pil)) {
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cs->exception_index = env->interrupt_index;
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sparc_cpu_do_interrupt(cs);
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return true;
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}
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}
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}
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return false;
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}
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static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info)
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{
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info->print_insn = print_insn_sparc;
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#ifdef TARGET_SPARC64
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info->mach = bfd_mach_sparc_v9b;
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#endif
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}
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static void sparc_cpu_parse_features(CPUState *cs, char *features,
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Error **errp);
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static int cpu_sparc_register(SPARCCPU *cpu, const char *cpu_model)
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{
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CPUSPARCState *env = &cpu->env;
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char *s = g_strdup(cpu_model);
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char *featurestr, *name = strtok(s, ",");
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sparc_def_t def1, *def = &def1;
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Error *err = NULL;
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if (cpu_sparc_find_by_name(def, name) < 0) {
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g_free(s);
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return -1;
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}
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env->def = g_memdup(def, sizeof(*def));
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featurestr = strtok(NULL, ",");
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sparc_cpu_parse_features(CPU(cpu), featurestr, &err);
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g_free(s);
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if (err) {
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error_report_err(err);
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return -1;
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}
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env->version = def->iu_version;
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env->fsr = def->fpu_version;
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env->nwindows = def->nwindows;
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#if !defined(TARGET_SPARC64)
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env->mmuregs[0] |= def->mmu_version;
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cpu_sparc_set_id(env, 0);
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env->mxccregs[7] |= def->mxcc_version;
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#else
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env->mmu_version = def->mmu_version;
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env->maxtl = def->maxtl;
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env->version |= def->maxtl << 8;
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env->version |= def->nwindows - 1;
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#endif
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return 0;
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}
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SPARCCPU *cpu_sparc_init(const char *cpu_model)
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{
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SPARCCPU *cpu;
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cpu = SPARC_CPU(object_new(TYPE_SPARC_CPU));
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if (cpu_sparc_register(cpu, cpu_model) < 0) {
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object_unref(OBJECT(cpu));
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return NULL;
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}
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object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
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return cpu;
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}
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void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
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{
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#if !defined(TARGET_SPARC64)
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env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
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#endif
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}
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static const sparc_def_t sparc_defs[] = {
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#ifdef TARGET_SPARC64
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{
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.name = "Fujitsu Sparc64",
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.iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 4,
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.maxtl = 4,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Fujitsu Sparc64 III",
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.iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 5,
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.maxtl = 4,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Fujitsu Sparc64 IV",
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.iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Fujitsu Sparc64 V",
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.iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI UltraSparc I",
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.iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI UltraSparc II",
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.iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI UltraSparc IIi",
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.iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI UltraSparc IIe",
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.iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Sun UltraSparc III",
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.iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Sun UltraSparc III Cu",
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.iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_3,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Sun UltraSparc IIIi",
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.iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Sun UltraSparc IV",
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.iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_4,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Sun UltraSparc IV+",
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.iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT,
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},
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{
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.name = "Sun UltraSparc IIIi+",
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.iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_3,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Sun UltraSparc T1",
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/* defined in sparc_ifu_fdp.v and ctu.h */
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.iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_sun4v,
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.nwindows = 8,
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.maxtl = 6,
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.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
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| CPU_FEATURE_GL,
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},
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{
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.name = "Sun UltraSparc T2",
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/* defined in tlu_asi_ctl.v and n2_revid_cust.v */
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.iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_sun4v,
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.nwindows = 8,
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.maxtl = 6,
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.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
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| CPU_FEATURE_GL,
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},
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{
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.name = "NEC UltraSparc I",
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.iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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#else
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{
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.name = "Fujitsu MB86904",
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.iu_version = 0x04 << 24, /* Impl 0, ver 4 */
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.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
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.mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0x00ffffc0,
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.mmu_cxr_mask = 0x000000ff,
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.mmu_sfsr_mask = 0x00016fff,
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.mmu_trcr_mask = 0x00ffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Fujitsu MB86907",
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.iu_version = 0x05 << 24, /* Impl 0, ver 5 */
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.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
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.mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0xffffffc0,
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.mmu_cxr_mask = 0x000000ff,
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.mmu_sfsr_mask = 0x00016fff,
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.mmu_trcr_mask = 0xffffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI MicroSparc I",
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.iu_version = 0x41000000,
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.fpu_version = 4 << 17,
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.mmu_version = 0x41000000,
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0x007ffff0,
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.mmu_cxr_mask = 0x0000003f,
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.mmu_sfsr_mask = 0x00016fff,
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.mmu_trcr_mask = 0x0000003f,
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.nwindows = 7,
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.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL |
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CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT |
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CPU_FEATURE_FMUL,
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},
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{
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.name = "TI MicroSparc II",
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.iu_version = 0x42000000,
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.fpu_version = 4 << 17,
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.mmu_version = 0x02000000,
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0x00ffffc0,
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.mmu_cxr_mask = 0x000000ff,
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.mmu_sfsr_mask = 0x00016fff,
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.mmu_trcr_mask = 0x00ffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI MicroSparc IIep",
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.iu_version = 0x42000000,
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.fpu_version = 4 << 17,
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.mmu_version = 0x04000000,
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0x00ffffc0,
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.mmu_cxr_mask = 0x000000ff,
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.mmu_sfsr_mask = 0x00016bff,
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.mmu_trcr_mask = 0x00ffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI SuperSparc 40", /* STP1020NPGA */
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.iu_version = 0x41000000, /* SuperSPARC 2.x */
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.fpu_version = 0 << 17,
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.mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */
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.mmu_bm = 0x00002000,
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.mmu_ctpr_mask = 0xffffffc0,
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.mmu_cxr_mask = 0x0000ffff,
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.mmu_sfsr_mask = 0xffffffff,
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.mmu_trcr_mask = 0xffffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI SuperSparc 50", /* STP1020PGA */
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.iu_version = 0x40000000, /* SuperSPARC 3.x */
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.fpu_version = 0 << 17,
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.mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
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.mmu_bm = 0x00002000,
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.mmu_ctpr_mask = 0xffffffc0,
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.mmu_cxr_mask = 0x0000ffff,
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.mmu_sfsr_mask = 0xffffffff,
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.mmu_trcr_mask = 0xffffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI SuperSparc 51",
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.iu_version = 0x40000000, /* SuperSPARC 3.x */
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.fpu_version = 0 << 17,
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.mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
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.mmu_bm = 0x00002000,
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.mmu_ctpr_mask = 0xffffffc0,
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.mmu_cxr_mask = 0x0000ffff,
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.mmu_sfsr_mask = 0xffffffff,
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.mmu_trcr_mask = 0xffffffff,
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.mxcc_version = 0x00000104,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI SuperSparc 60", /* STP1020APGA */
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.iu_version = 0x40000000, /* SuperSPARC 3.x */
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.fpu_version = 0 << 17,
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.mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
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.mmu_bm = 0x00002000,
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.mmu_ctpr_mask = 0xffffffc0,
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.mmu_cxr_mask = 0x0000ffff,
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.mmu_sfsr_mask = 0xffffffff,
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.mmu_trcr_mask = 0xffffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI SuperSparc 61",
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.iu_version = 0x44000000, /* SuperSPARC 3.x */
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.fpu_version = 0 << 17,
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.mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
|
|
.mmu_bm = 0x00002000,
|
|
.mmu_ctpr_mask = 0xffffffc0,
|
|
.mmu_cxr_mask = 0x0000ffff,
|
|
.mmu_sfsr_mask = 0xffffffff,
|
|
.mmu_trcr_mask = 0xffffffff,
|
|
.mxcc_version = 0x00000104,
|
|
.nwindows = 8,
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
},
|
|
{
|
|
.name = "TI SuperSparc II",
|
|
.iu_version = 0x40000000, /* SuperSPARC II 1.x */
|
|
.fpu_version = 0 << 17,
|
|
.mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */
|
|
.mmu_bm = 0x00002000,
|
|
.mmu_ctpr_mask = 0xffffffc0,
|
|
.mmu_cxr_mask = 0x0000ffff,
|
|
.mmu_sfsr_mask = 0xffffffff,
|
|
.mmu_trcr_mask = 0xffffffff,
|
|
.mxcc_version = 0x00000104,
|
|
.nwindows = 8,
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
},
|
|
{
|
|
.name = "LEON2",
|
|
.iu_version = 0xf2000000,
|
|
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
|
|
.mmu_version = 0xf2000000,
|
|
.mmu_bm = 0x00004000,
|
|
.mmu_ctpr_mask = 0x007ffff0,
|
|
.mmu_cxr_mask = 0x0000003f,
|
|
.mmu_sfsr_mask = 0xffffffff,
|
|
.mmu_trcr_mask = 0xffffffff,
|
|
.nwindows = 8,
|
|
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN,
|
|
},
|
|
{
|
|
.name = "LEON3",
|
|
.iu_version = 0xf3000000,
|
|
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
|
|
.mmu_version = 0xf3000000,
|
|
.mmu_bm = 0x00000000,
|
|
.mmu_ctpr_mask = 0xfffffffc,
|
|
.mmu_cxr_mask = 0x000000ff,
|
|
.mmu_sfsr_mask = 0xffffffff,
|
|
.mmu_trcr_mask = 0xffffffff,
|
|
.nwindows = 8,
|
|
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN |
|
|
CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWERDOWN |
|
|
CPU_FEATURE_CASA,
|
|
},
|
|
#endif
|
|
};
|
|
|
|
static const char * const feature_name[] = {
|
|
"float",
|
|
"float128",
|
|
"swap",
|
|
"mul",
|
|
"div",
|
|
"flush",
|
|
"fsqrt",
|
|
"fmul",
|
|
"vis1",
|
|
"vis2",
|
|
"fsmuld",
|
|
"hypv",
|
|
"cmt",
|
|
"gl",
|
|
};
|
|
|
|
static void print_features(FILE *f, fprintf_function cpu_fprintf,
|
|
uint32_t features, const char *prefix)
|
|
{
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(feature_name); i++) {
|
|
if (feature_name[i] && (features & (1 << i))) {
|
|
if (prefix) {
|
|
(*cpu_fprintf)(f, "%s", prefix);
|
|
}
|
|
(*cpu_fprintf)(f, "%s ", feature_name[i]);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features)
|
|
{
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(feature_name); i++) {
|
|
if (feature_name[i] && !strcmp(flagname, feature_name[i])) {
|
|
*features |= 1 << i;
|
|
return;
|
|
}
|
|
}
|
|
error_report("CPU feature %s not found", flagname);
|
|
}
|
|
|
|
static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *name)
|
|
{
|
|
unsigned int i;
|
|
const sparc_def_t *def = NULL;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
|
|
if (strcasecmp(name, sparc_defs[i].name) == 0) {
|
|
def = &sparc_defs[i];
|
|
}
|
|
}
|
|
if (!def) {
|
|
return -1;
|
|
}
|
|
memcpy(cpu_def, def, sizeof(*def));
|
|
return 0;
|
|
}
|
|
|
|
static void sparc_cpu_parse_features(CPUState *cs, char *features,
|
|
Error **errp)
|
|
{
|
|
SPARCCPU *cpu = SPARC_CPU(cs);
|
|
sparc_def_t *cpu_def = cpu->env.def;
|
|
char *featurestr;
|
|
uint32_t plus_features = 0;
|
|
uint32_t minus_features = 0;
|
|
uint64_t iu_version;
|
|
uint32_t fpu_version, mmu_version, nwindows;
|
|
|
|
featurestr = features ? strtok(features, ",") : NULL;
|
|
while (featurestr) {
|
|
char *val;
|
|
|
|
if (featurestr[0] == '+') {
|
|
add_flagname_to_bitmaps(featurestr + 1, &plus_features);
|
|
} else if (featurestr[0] == '-') {
|
|
add_flagname_to_bitmaps(featurestr + 1, &minus_features);
|
|
} else if ((val = strchr(featurestr, '='))) {
|
|
*val = 0; val++;
|
|
if (!strcmp(featurestr, "iu_version")) {
|
|
char *err;
|
|
|
|
iu_version = strtoll(val, &err, 0);
|
|
if (!*val || *err) {
|
|
error_setg(errp, "bad numerical value %s", val);
|
|
return;
|
|
}
|
|
cpu_def->iu_version = iu_version;
|
|
#ifdef DEBUG_FEATURES
|
|
fprintf(stderr, "iu_version %" PRIx64 "\n", iu_version);
|
|
#endif
|
|
} else if (!strcmp(featurestr, "fpu_version")) {
|
|
char *err;
|
|
|
|
fpu_version = strtol(val, &err, 0);
|
|
if (!*val || *err) {
|
|
error_setg(errp, "bad numerical value %s", val);
|
|
return;
|
|
}
|
|
cpu_def->fpu_version = fpu_version;
|
|
#ifdef DEBUG_FEATURES
|
|
fprintf(stderr, "fpu_version %x\n", fpu_version);
|
|
#endif
|
|
} else if (!strcmp(featurestr, "mmu_version")) {
|
|
char *err;
|
|
|
|
mmu_version = strtol(val, &err, 0);
|
|
if (!*val || *err) {
|
|
error_setg(errp, "bad numerical value %s", val);
|
|
return;
|
|
}
|
|
cpu_def->mmu_version = mmu_version;
|
|
#ifdef DEBUG_FEATURES
|
|
fprintf(stderr, "mmu_version %x\n", mmu_version);
|
|
#endif
|
|
} else if (!strcmp(featurestr, "nwindows")) {
|
|
char *err;
|
|
|
|
nwindows = strtol(val, &err, 0);
|
|
if (!*val || *err || nwindows > MAX_NWINDOWS ||
|
|
nwindows < MIN_NWINDOWS) {
|
|
error_setg(errp, "bad numerical value %s", val);
|
|
return;
|
|
}
|
|
cpu_def->nwindows = nwindows;
|
|
#ifdef DEBUG_FEATURES
|
|
fprintf(stderr, "nwindows %d\n", nwindows);
|
|
#endif
|
|
} else {
|
|
error_setg(errp, "unrecognized feature %s", featurestr);
|
|
return;
|
|
}
|
|
} else {
|
|
error_setg(errp, "feature string `%s' not in format "
|
|
"(+feature|-feature|feature=xyz)", featurestr);
|
|
return;
|
|
}
|
|
featurestr = strtok(NULL, ",");
|
|
}
|
|
cpu_def->features |= plus_features;
|
|
cpu_def->features &= ~minus_features;
|
|
#ifdef DEBUG_FEATURES
|
|
print_features(stderr, fprintf, cpu_def->features, NULL);
|
|
#endif
|
|
}
|
|
|
|
void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
|
|
{
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
|
|
(*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx
|
|
" FPU %08x MMU %08x NWINS %d ",
|
|
sparc_defs[i].name,
|
|
sparc_defs[i].iu_version,
|
|
sparc_defs[i].fpu_version,
|
|
sparc_defs[i].mmu_version,
|
|
sparc_defs[i].nwindows);
|
|
print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES &
|
|
~sparc_defs[i].features, "-");
|
|
print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES &
|
|
sparc_defs[i].features, "+");
|
|
(*cpu_fprintf)(f, "\n");
|
|
}
|
|
(*cpu_fprintf)(f, "Default CPU feature flags (use '-' to remove): ");
|
|
print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES, NULL);
|
|
(*cpu_fprintf)(f, "\n");
|
|
(*cpu_fprintf)(f, "Available CPU feature flags (use '+' to add): ");
|
|
print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES, NULL);
|
|
(*cpu_fprintf)(f, "\n");
|
|
(*cpu_fprintf)(f, "Numerical features (use '=' to set): iu_version "
|
|
"fpu_version mmu_version nwindows\n");
|
|
}
|
|
|
|
static void cpu_print_cc(FILE *f, fprintf_function cpu_fprintf,
|
|
uint32_t cc)
|
|
{
|
|
cpu_fprintf(f, "%c%c%c%c", cc & PSR_NEG ? 'N' : '-',
|
|
cc & PSR_ZERO ? 'Z' : '-', cc & PSR_OVF ? 'V' : '-',
|
|
cc & PSR_CARRY ? 'C' : '-');
|
|
}
|
|
|
|
#ifdef TARGET_SPARC64
|
|
#define REGS_PER_LINE 4
|
|
#else
|
|
#define REGS_PER_LINE 8
|
|
#endif
|
|
|
|
void sparc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
|
|
int flags)
|
|
{
|
|
SPARCCPU *cpu = SPARC_CPU(cs);
|
|
CPUSPARCState *env = &cpu->env;
|
|
int i, x;
|
|
|
|
cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc,
|
|
env->npc);
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
if (i % REGS_PER_LINE == 0) {
|
|
cpu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1);
|
|
}
|
|
cpu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]);
|
|
if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
|
|
cpu_fprintf(f, "\n");
|
|
}
|
|
}
|
|
for (x = 0; x < 3; x++) {
|
|
for (i = 0; i < 8; i++) {
|
|
if (i % REGS_PER_LINE == 0) {
|
|
cpu_fprintf(f, "%%%c%d-%d: ",
|
|
x == 0 ? 'o' : (x == 1 ? 'l' : 'i'),
|
|
i, i + REGS_PER_LINE - 1);
|
|
}
|
|
cpu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]);
|
|
if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
|
|
cpu_fprintf(f, "\n");
|
|
}
|
|
}
|
|
}
|
|
|
|
for (i = 0; i < TARGET_DPREGS; i++) {
|
|
if ((i & 3) == 0) {
|
|
cpu_fprintf(f, "%%f%02d: ", i * 2);
|
|
}
|
|
cpu_fprintf(f, " %016" PRIx64, env->fpr[i].ll);
|
|
if ((i & 3) == 3) {
|
|
cpu_fprintf(f, "\n");
|
|
}
|
|
}
|
|
#ifdef TARGET_SPARC64
|
|
cpu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate,
|
|
(unsigned)cpu_get_ccr(env));
|
|
cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << PSR_CARRY_SHIFT);
|
|
cpu_fprintf(f, " xcc: ");
|
|
cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4));
|
|
cpu_fprintf(f, ") asi: %02x tl: %d pil: %x gl: %d\n", env->asi, env->tl,
|
|
env->psrpil, env->gl);
|
|
cpu_fprintf(f, "tbr: " TARGET_FMT_lx " hpstate: " TARGET_FMT_lx " htba: "
|
|
TARGET_FMT_lx "\n", env->tbr, env->hpstate, env->htba);
|
|
cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d "
|
|
"cleanwin: %d cwp: %d\n",
|
|
env->cansave, env->canrestore, env->otherwin, env->wstate,
|
|
env->cleanwin, env->nwindows - 1 - env->cwp);
|
|
cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: "
|
|
TARGET_FMT_lx "\n", env->fsr, env->y, env->fprs);
|
|
|
|
#else
|
|
cpu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env));
|
|
cpu_print_cc(f, cpu_fprintf, cpu_get_psr(env));
|
|
cpu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs ? 'S' : '-',
|
|
env->psrps ? 'P' : '-', env->psret ? 'E' : '-',
|
|
env->wim);
|
|
cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n",
|
|
env->fsr, env->y);
|
|
#endif
|
|
cpu_fprintf(f, "\n");
|
|
}
|
|
|
|
static void sparc_cpu_set_pc(CPUState *cs, vaddr value)
|
|
{
|
|
SPARCCPU *cpu = SPARC_CPU(cs);
|
|
|
|
cpu->env.pc = value;
|
|
cpu->env.npc = value + 4;
|
|
}
|
|
|
|
static void sparc_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
|
|
{
|
|
SPARCCPU *cpu = SPARC_CPU(cs);
|
|
|
|
cpu->env.pc = tb->pc;
|
|
cpu->env.npc = tb->cs_base;
|
|
}
|
|
|
|
static bool sparc_cpu_has_work(CPUState *cs)
|
|
{
|
|
SPARCCPU *cpu = SPARC_CPU(cs);
|
|
CPUSPARCState *env = &cpu->env;
|
|
|
|
return (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
|
|
cpu_interrupts_enabled(env);
|
|
}
|
|
|
|
static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
|
|
{
|
|
CPUState *cs = CPU(dev);
|
|
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev);
|
|
Error *local_err = NULL;
|
|
#if defined(CONFIG_USER_ONLY)
|
|
SPARCCPU *cpu = SPARC_CPU(dev);
|
|
CPUSPARCState *env = &cpu->env;
|
|
|
|
if ((env->def->features & CPU_FEATURE_FLOAT)) {
|
|
env->def->features |= CPU_FEATURE_FLOAT128;
|
|
}
|
|
#endif
|
|
|
|
cpu_exec_realizefn(cs, &local_err);
|
|
if (local_err != NULL) {
|
|
error_propagate(errp, local_err);
|
|
return;
|
|
}
|
|
|
|
qemu_init_vcpu(cs);
|
|
|
|
scc->parent_realize(dev, errp);
|
|
}
|
|
|
|
static void sparc_cpu_initfn(Object *obj)
|
|
{
|
|
CPUState *cs = CPU(obj);
|
|
SPARCCPU *cpu = SPARC_CPU(obj);
|
|
CPUSPARCState *env = &cpu->env;
|
|
|
|
cs->env_ptr = env;
|
|
|
|
if (tcg_enabled()) {
|
|
gen_intermediate_code_init(env);
|
|
}
|
|
}
|
|
|
|
static void sparc_cpu_uninitfn(Object *obj)
|
|
{
|
|
SPARCCPU *cpu = SPARC_CPU(obj);
|
|
CPUSPARCState *env = &cpu->env;
|
|
|
|
g_free(env->def);
|
|
}
|
|
|
|
static void sparc_cpu_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
|
|
CPUClass *cc = CPU_CLASS(oc);
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
scc->parent_realize = dc->realize;
|
|
dc->realize = sparc_cpu_realizefn;
|
|
|
|
scc->parent_reset = cc->reset;
|
|
cc->reset = sparc_cpu_reset;
|
|
|
|
cc->has_work = sparc_cpu_has_work;
|
|
cc->do_interrupt = sparc_cpu_do_interrupt;
|
|
cc->cpu_exec_interrupt = sparc_cpu_exec_interrupt;
|
|
cc->dump_state = sparc_cpu_dump_state;
|
|
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
|
|
cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
|
|
#endif
|
|
cc->set_pc = sparc_cpu_set_pc;
|
|
cc->synchronize_from_tb = sparc_cpu_synchronize_from_tb;
|
|
cc->gdb_read_register = sparc_cpu_gdb_read_register;
|
|
cc->gdb_write_register = sparc_cpu_gdb_write_register;
|
|
#ifdef CONFIG_USER_ONLY
|
|
cc->handle_mmu_fault = sparc_cpu_handle_mmu_fault;
|
|
#else
|
|
cc->do_unassigned_access = sparc_cpu_unassigned_access;
|
|
cc->do_unaligned_access = sparc_cpu_do_unaligned_access;
|
|
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
|
|
cc->vmsd = &vmstate_sparc_cpu;
|
|
#endif
|
|
cc->disas_set_info = cpu_sparc_disas_set_info;
|
|
|
|
#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
|
|
cc->gdb_num_core_regs = 86;
|
|
#else
|
|
cc->gdb_num_core_regs = 72;
|
|
#endif
|
|
}
|
|
|
|
static const TypeInfo sparc_cpu_type_info = {
|
|
.name = TYPE_SPARC_CPU,
|
|
.parent = TYPE_CPU,
|
|
.instance_size = sizeof(SPARCCPU),
|
|
.instance_init = sparc_cpu_initfn,
|
|
.instance_finalize = sparc_cpu_uninitfn,
|
|
.abstract = false,
|
|
.class_size = sizeof(SPARCCPUClass),
|
|
.class_init = sparc_cpu_class_init,
|
|
};
|
|
|
|
static void sparc_cpu_register_types(void)
|
|
{
|
|
type_register_static(&sparc_cpu_type_info);
|
|
}
|
|
|
|
type_init(sparc_cpu_register_types)
|