Richard Henderson e0a369cf88 target/openrisc: Fix singlestep_enabled ... We failed to store to cpu_pc before raising the exception, which caused us to re-execute the same insn that we stepped. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>		2018-07-03 00:05:28 +09:00
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alpha
arm	target/arm: Add ID_ISAR6	2018-06-29 15:30:54 +01:00
cris
hppa
i386	* "info mtree" improvements (Alexey)	2018-06-29 12:30:29 +01:00
lm32
m68k
microblaze	target-microblaze: Rework NOP/zero instruction handling	2018-06-15 09:05:00 +02:00
mips	target/mips: Fix gdbstub to read/write 64 bit FP registers	2018-06-27 20:13:50 +02:00
moxie
nios2
openrisc	target/openrisc: Fix singlestep_enabled	2018-07-03 00:05:28 +09:00
ppc	compiler: add a sizeof_field() macro	2018-06-27 13:01:40 +01:00
riscv
s390x	compiler: add a sizeof_field() macro	2018-06-27 13:01:40 +01:00
sh4
sparc	SPARC64: add icount support	2018-06-17 11:13:06 +01:00
tilegx
tricore
unicore32
xtensa	xtensa: Avoid calling get_page_addr_code() from helper function	2018-06-30 12:00:17 -07:00