Bin Meng 19800265d4 hw/riscv: virt: Map high mmio for PCIe ... Some peripherals require 64-bit PCI address, so let's map the high mmio space for PCIe. For RV32, the address is hardcoded to below 4 GiB from the highest accessible physical address. For RV64, the base address depends on top of RAM and is aligned to its size which is using 16 GiB for now. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210220144807.819-5-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-03-04 09:43:29 -05:00
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Kconfig	hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card	2021-03-04 09:43:29 -05:00
boot.c	riscv: Pass RISCVHartArrayState by pointer	2021-01-16 14:34:46 -08:00
meson.build	hw/riscv: Always build riscv_hart.c	2020-09-09 15:54:19 -07:00
microchip_pfsoc.c	hw/riscv: Drop 'struct MemmapEntry'	2021-03-04 09:43:29 -05:00
numa.c	hw/riscv: Add helpers for RISC-V multi-socket NUMA machines	2020-08-25 09:11:35 -07:00
opentitan.c	hw/riscv: Drop 'struct MemmapEntry'	2021-03-04 09:43:29 -05:00
riscv_hart.c	hw/riscv: hart: Add a new 'resetvec' property	2020-09-09 15:54:18 -07:00
sifive_e.c	hw/riscv: Drop 'struct MemmapEntry'	2021-03-04 09:43:29 -05:00
sifive_u.c	hw/riscv: Drop 'struct MemmapEntry'	2021-03-04 09:43:29 -05:00
spike.c	hw/riscv: Drop 'struct MemmapEntry'	2021-03-04 09:43:29 -05:00
virt.c	hw/riscv: virt: Map high mmio for PCIe	2021-03-04 09:43:29 -05:00