87ecb68bdf
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3674 c046a42c-6fe2-441c-8c8c-71466251a162
145 lines
3.7 KiB
C
145 lines
3.7 KiB
C
/*
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* ARM Versatile/PB PCI host controller
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*
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* Copyright (c) 2006 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licenced under the LGPL.
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*/
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#include "hw.h"
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#include "pci.h"
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#include "primecell.h"
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static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr)
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{
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return addr & 0xffffff;
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}
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static void pci_vpb_config_writeb (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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pci_data_write(opaque, vpb_pci_config_addr (addr), val, 1);
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}
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static void pci_vpb_config_writew (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap16(val);
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#endif
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pci_data_write(opaque, vpb_pci_config_addr (addr), val, 2);
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}
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static void pci_vpb_config_writel (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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pci_data_write(opaque, vpb_pci_config_addr (addr), val, 4);
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}
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static uint32_t pci_vpb_config_readb (void *opaque, target_phys_addr_t addr)
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{
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uint32_t val;
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val = pci_data_read(opaque, vpb_pci_config_addr (addr), 1);
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return val;
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}
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static uint32_t pci_vpb_config_readw (void *opaque, target_phys_addr_t addr)
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{
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uint32_t val;
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val = pci_data_read(opaque, vpb_pci_config_addr (addr), 2);
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap16(val);
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#endif
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return val;
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}
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static uint32_t pci_vpb_config_readl (void *opaque, target_phys_addr_t addr)
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{
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uint32_t val;
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val = pci_data_read(opaque, vpb_pci_config_addr (addr), 4);
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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return val;
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}
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static CPUWriteMemoryFunc *pci_vpb_config_write[] = {
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&pci_vpb_config_writeb,
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&pci_vpb_config_writew,
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&pci_vpb_config_writel,
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};
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static CPUReadMemoryFunc *pci_vpb_config_read[] = {
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&pci_vpb_config_readb,
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&pci_vpb_config_readw,
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&pci_vpb_config_readl,
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};
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static int pci_vpb_irq;
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static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
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{
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return irq_num;
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}
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static void pci_vpb_set_irq(qemu_irq *pic, int irq_num, int level)
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{
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qemu_set_irq(pic[pci_vpb_irq + irq_num], level);
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}
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PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview)
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{
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PCIBus *s;
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PCIDevice *d;
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int mem_config;
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uint32_t base;
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const char * name;
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pci_vpb_irq = irq;
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if (realview) {
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base = 0x60000000;
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name = "RealView EB PCI Controller";
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} else {
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base = 0x40000000;
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name = "Versatile/PB PCI Controller";
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}
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s = pci_register_bus(pci_vpb_set_irq, pci_vpb_map_irq, pic, 11 << 3, 4);
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/* ??? Register memory space. */
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mem_config = cpu_register_io_memory(0, pci_vpb_config_read,
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pci_vpb_config_write, s);
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/* Selfconfig area. */
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cpu_register_physical_memory(base + 0x01000000, 0x1000000, mem_config);
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/* Normal config area. */
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cpu_register_physical_memory(base + 0x02000000, 0x1000000, mem_config);
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d = pci_register_device(s, name, sizeof(PCIDevice), -1, NULL, NULL);
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if (realview) {
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/* IO memory area. */
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isa_mmio_init(base + 0x03000000, 0x00100000);
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}
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d->config[0x00] = 0xee; // vendor_id
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d->config[0x01] = 0x10;
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/* Both boards have the same device ID. Oh well. */
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d->config[0x02] = 0x00; // device_id
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d->config[0x03] = 0x03;
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d->config[0x04] = 0x00;
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d->config[0x05] = 0x00;
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d->config[0x06] = 0x20;
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d->config[0x07] = 0x02;
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d->config[0x08] = 0x00; // revision
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d->config[0x09] = 0x00; // programming i/f
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d->config[0x0A] = 0x40; // class_sub = pci host
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d->config[0x0B] = 0x0b; // class_base = PCI_bridge
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d->config[0x0D] = 0x10; // latency_timer
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return s;
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}
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