Hesham Almatary e0f8fa72de RISC-V: Only Check PMP if MMU translation succeeds ... The current implementation unnecessarily checks for PMP even if MMU translation failed. This may trigger a wrong PMP access exception instead of a page exception. For example, the very first instruction fetched after the first satp write in S-Mode will trigger a PMP access fault instead of an instruction fetch page fault. This patch prioritises MMU exceptions over PMP exceptions and only checks for PMP if MMU translation succeeds. This patch is required for future commits that properly report PMP exception violations if PTW succeeds. Signed-off-by: Hesham Almatary <Hesham.Almatary@cl.cam.ac.uk> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2019-06-23 23:44:41 -07:00
..
insn_trans	target/riscv: Split gen_arith_imm into functional and temp	2019-05-24 12:09:23 -07:00
Makefile.objs	target/riscv: Split RVC32 and RVC64 insns into separate files	2019-05-24 12:09:22 -07:00
cpu-param.h	tcg: Split out target/arch/cpu-param.h	2019-06-10 07:03:34 -07:00
cpu.c	target/riscv: Implement riscv_cpu_unassigned_access	2019-06-23 23:44:41 -07:00
cpu.h	target/riscv: Implement riscv_cpu_unassigned_access	2019-06-23 23:44:41 -07:00
cpu_bits.h	Supply missing header guards	2019-06-12 13:20:21 +02:00
cpu_helper.c	RISC-V: Only Check PMP if MMU translation succeeds	2019-06-23 23:44:41 -07:00
cpu_user.h	Supply missing header guards	2019-06-12 13:20:21 +02:00
csr.c	target/riscv: Use env_cpu, env_archcpu	2019-06-10 07:03:42 -07:00
fpu_helper.c	RISC-V: Use riscv prefix consistently on cpu helpers	2019-02-11 15:56:21 -08:00
gdbstub.c	Include qemu-common.h exactly where needed	2019-06-12 13:20:20 +02:00
helper.h	RISC-V CPU Helpers	2018-03-07 08:30:28 +13:00
insn16-32.decode	target/riscv: Split RVC32 and RVC64 insns into separate files	2019-05-24 12:09:22 -07:00
insn16-64.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-24 12:09:25 -07:00
insn16.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-24 12:09:25 -07:00
insn32-64.decode	target/riscv: Convert RV64D insns to decodetree	2019-03-13 10:34:06 +01:00
insn32.decode	target/riscv: Name the argument sets for all of insn32 formats	2019-05-24 12:09:22 -07:00
instmap.h	Supply missing header guards	2019-06-12 13:20:21 +02:00
op_helper.c	target/riscv: Use env_cpu, env_archcpu	2019-06-10 07:03:42 -07:00
pmp.c	target/riscv: Fix PMP range boundary address bug	2019-06-23 23:44:41 -07:00
pmp.h	Clean up ill-advised or unusual header guards	2019-05-13 08:58:55 +02:00
trace-events	RISC-V: Convert trap debugging to trace events	2019-03-19 05:14:40 -07:00
translate.c	target/riscv: Split gen_arith_imm into functional and temp	2019-05-24 12:09:23 -07:00