434 lines
14 KiB
C
434 lines
14 KiB
C
/*
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* QEMU model of XGMAC Ethernet.
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*
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* derived from the Xilinx AXI-Ethernet by Edgar E. Iglesias.
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*
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* Copyright (c) 2011 Calxeda, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/sysbus.h"
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#include "sysemu/char.h"
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#include "qemu/log.h"
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#include "net/net.h"
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#include "net/checksum.h"
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#ifdef DEBUG_XGMAC
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#define DEBUGF_BRK(message, args...) do { \
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fprintf(stderr, (message), ## args); \
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} while (0)
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#else
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#define DEBUGF_BRK(message, args...) do { } while (0)
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#endif
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#define XGMAC_CONTROL 0x00000000 /* MAC Configuration */
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#define XGMAC_FRAME_FILTER 0x00000001 /* MAC Frame Filter */
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#define XGMAC_FLOW_CTRL 0x00000006 /* MAC Flow Control */
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#define XGMAC_VLAN_TAG 0x00000007 /* VLAN Tags */
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#define XGMAC_VERSION 0x00000008 /* Version */
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/* VLAN tag for insertion or replacement into tx frames */
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#define XGMAC_VLAN_INCL 0x00000009
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#define XGMAC_LPI_CTRL 0x0000000a /* LPI Control and Status */
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#define XGMAC_LPI_TIMER 0x0000000b /* LPI Timers Control */
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#define XGMAC_TX_PACE 0x0000000c /* Transmit Pace and Stretch */
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#define XGMAC_VLAN_HASH 0x0000000d /* VLAN Hash Table */
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#define XGMAC_DEBUG 0x0000000e /* Debug */
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#define XGMAC_INT_STATUS 0x0000000f /* Interrupt and Control */
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/* HASH table registers */
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#define XGMAC_HASH(n) ((0x00000300/4) + (n))
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#define XGMAC_NUM_HASH 16
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/* Operation Mode */
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#define XGMAC_OPMODE (0x00000400/4)
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/* Remote Wake-Up Frame Filter */
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#define XGMAC_REMOTE_WAKE (0x00000700/4)
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/* PMT Control and Status */
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#define XGMAC_PMT (0x00000704/4)
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#define XGMAC_ADDR_HIGH(reg) (0x00000010+((reg) * 2))
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#define XGMAC_ADDR_LOW(reg) (0x00000011+((reg) * 2))
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#define DMA_BUS_MODE 0x000003c0 /* Bus Mode */
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#define DMA_XMT_POLL_DEMAND 0x000003c1 /* Transmit Poll Demand */
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#define DMA_RCV_POLL_DEMAND 0x000003c2 /* Received Poll Demand */
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#define DMA_RCV_BASE_ADDR 0x000003c3 /* Receive List Base */
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#define DMA_TX_BASE_ADDR 0x000003c4 /* Transmit List Base */
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#define DMA_STATUS 0x000003c5 /* Status Register */
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#define DMA_CONTROL 0x000003c6 /* Ctrl (Operational Mode) */
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#define DMA_INTR_ENA 0x000003c7 /* Interrupt Enable */
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#define DMA_MISSED_FRAME_CTR 0x000003c8 /* Missed Frame Counter */
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/* Receive Interrupt Watchdog Timer */
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#define DMA_RI_WATCHDOG_TIMER 0x000003c9
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#define DMA_AXI_BUS 0x000003ca /* AXI Bus Mode */
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#define DMA_AXI_STATUS 0x000003cb /* AXI Status */
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#define DMA_CUR_TX_DESC_ADDR 0x000003d2 /* Current Host Tx Descriptor */
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#define DMA_CUR_RX_DESC_ADDR 0x000003d3 /* Current Host Rx Descriptor */
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#define DMA_CUR_TX_BUF_ADDR 0x000003d4 /* Current Host Tx Buffer */
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#define DMA_CUR_RX_BUF_ADDR 0x000003d5 /* Current Host Rx Buffer */
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#define DMA_HW_FEATURE 0x000003d6 /* Enabled Hardware Features */
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/* DMA Status register defines */
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#define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */
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#define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */
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#define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */
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#define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */
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#define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */
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#define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */
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#define DMA_STATUS_TS_SHIFT 20
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#define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */
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#define DMA_STATUS_RS_SHIFT 17
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#define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */
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#define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */
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#define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */
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#define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */
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#define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */
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#define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */
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#define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */
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#define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */
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#define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */
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#define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */
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#define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */
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#define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */
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#define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavailable */
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#define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */
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#define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
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/* DMA Control register defines */
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#define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */
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#define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
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#define DMA_CONTROL_DFF 0x01000000 /* Disable flush of rx frames */
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struct desc {
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uint32_t ctl_stat;
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uint16_t buffer1_size;
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uint16_t buffer2_size;
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uint32_t buffer1_addr;
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uint32_t buffer2_addr;
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uint32_t ext_stat;
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uint32_t res[3];
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};
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#define R_MAX 0x400
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typedef struct RxTxStats {
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uint64_t rx_bytes;
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uint64_t tx_bytes;
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uint64_t rx;
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uint64_t rx_bcast;
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uint64_t rx_mcast;
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} RxTxStats;
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typedef struct XgmacState {
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SysBusDevice busdev;
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MemoryRegion iomem;
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qemu_irq sbd_irq;
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qemu_irq pmt_irq;
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qemu_irq mci_irq;
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NICState *nic;
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NICConf conf;
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struct RxTxStats stats;
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uint32_t regs[R_MAX];
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} XgmacState;
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const VMStateDescription vmstate_rxtx_stats = {
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.name = "xgmac_stats",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(rx_bytes, RxTxStats),
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VMSTATE_UINT64(tx_bytes, RxTxStats),
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VMSTATE_UINT64(rx, RxTxStats),
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VMSTATE_UINT64(rx_bcast, RxTxStats),
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VMSTATE_UINT64(rx_mcast, RxTxStats),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_xgmac = {
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.name = "xgmac",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_STRUCT(stats, XgmacState, 0, vmstate_rxtx_stats, RxTxStats),
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VMSTATE_UINT32_ARRAY(regs, XgmacState, R_MAX),
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VMSTATE_END_OF_LIST()
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}
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};
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static void xgmac_read_desc(struct XgmacState *s, struct desc *d, int rx)
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{
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uint32_t addr = rx ? s->regs[DMA_CUR_RX_DESC_ADDR] :
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s->regs[DMA_CUR_TX_DESC_ADDR];
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cpu_physical_memory_read(addr, d, sizeof(*d));
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}
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static void xgmac_write_desc(struct XgmacState *s, struct desc *d, int rx)
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{
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int reg = rx ? DMA_CUR_RX_DESC_ADDR : DMA_CUR_TX_DESC_ADDR;
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uint32_t addr = s->regs[reg];
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if (!rx && (d->ctl_stat & 0x00200000)) {
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s->regs[reg] = s->regs[DMA_TX_BASE_ADDR];
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} else if (rx && (d->buffer1_size & 0x8000)) {
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s->regs[reg] = s->regs[DMA_RCV_BASE_ADDR];
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} else {
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s->regs[reg] += sizeof(*d);
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}
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cpu_physical_memory_write(addr, d, sizeof(*d));
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}
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static void xgmac_enet_send(struct XgmacState *s)
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{
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struct desc bd;
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int frame_size;
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int len;
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uint8_t frame[8192];
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uint8_t *ptr;
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ptr = frame;
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frame_size = 0;
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while (1) {
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xgmac_read_desc(s, &bd, 0);
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if ((bd.ctl_stat & 0x80000000) == 0) {
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/* Run out of descriptors to transmit. */
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break;
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}
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len = (bd.buffer1_size & 0xfff) + (bd.buffer2_size & 0xfff);
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if ((bd.buffer1_size & 0xfff) > 2048) {
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DEBUGF_BRK("qemu:%s:ERROR...ERROR...ERROR... -- "
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"xgmac buffer 1 len on send > 2048 (0x%x)\n",
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__func__, bd.buffer1_size & 0xfff);
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}
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if ((bd.buffer2_size & 0xfff) != 0) {
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DEBUGF_BRK("qemu:%s:ERROR...ERROR...ERROR... -- "
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"xgmac buffer 2 len on send != 0 (0x%x)\n",
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__func__, bd.buffer2_size & 0xfff);
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}
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if (len >= sizeof(frame)) {
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DEBUGF_BRK("qemu:%s: buffer overflow %d read into %zu "
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"buffer\n" , __func__, len, sizeof(frame));
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DEBUGF_BRK("qemu:%s: buffer1.size=%d; buffer2.size=%d\n",
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__func__, bd.buffer1_size, bd.buffer2_size);
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}
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cpu_physical_memory_read(bd.buffer1_addr, ptr, len);
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ptr += len;
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frame_size += len;
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if (bd.ctl_stat & 0x20000000) {
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/* Last buffer in frame. */
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qemu_send_packet(qemu_get_queue(s->nic), frame, len);
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ptr = frame;
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frame_size = 0;
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s->regs[DMA_STATUS] |= DMA_STATUS_TI | DMA_STATUS_NIS;
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}
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bd.ctl_stat &= ~0x80000000;
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/* Write back the modified descriptor. */
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xgmac_write_desc(s, &bd, 0);
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}
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}
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static void enet_update_irq(struct XgmacState *s)
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{
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int stat = s->regs[DMA_STATUS] & s->regs[DMA_INTR_ENA];
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qemu_set_irq(s->sbd_irq, !!stat);
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}
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static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size)
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{
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struct XgmacState *s = opaque;
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uint64_t r = 0;
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addr >>= 2;
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switch (addr) {
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case XGMAC_VERSION:
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r = 0x1012;
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break;
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default:
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if (addr < ARRAY_SIZE(s->regs)) {
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r = s->regs[addr];
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}
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break;
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}
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return r;
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}
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static void enet_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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struct XgmacState *s = opaque;
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addr >>= 2;
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switch (addr) {
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case DMA_BUS_MODE:
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s->regs[DMA_BUS_MODE] = value & ~0x1;
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break;
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case DMA_XMT_POLL_DEMAND:
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xgmac_enet_send(s);
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break;
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case DMA_STATUS:
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s->regs[DMA_STATUS] = s->regs[DMA_STATUS] & ~value;
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break;
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case DMA_RCV_BASE_ADDR:
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s->regs[DMA_RCV_BASE_ADDR] = s->regs[DMA_CUR_RX_DESC_ADDR] = value;
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break;
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case DMA_TX_BASE_ADDR:
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s->regs[DMA_TX_BASE_ADDR] = s->regs[DMA_CUR_TX_DESC_ADDR] = value;
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break;
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default:
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if (addr < ARRAY_SIZE(s->regs)) {
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s->regs[addr] = value;
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}
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break;
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}
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enet_update_irq(s);
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}
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static const MemoryRegionOps enet_mem_ops = {
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.read = enet_read,
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.write = enet_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static int eth_can_rx(NetClientState *nc)
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{
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struct XgmacState *s = qemu_get_nic_opaque(nc);
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/* RX enabled? */
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return s->regs[DMA_CONTROL] & DMA_CONTROL_SR;
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}
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static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
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{
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struct XgmacState *s = qemu_get_nic_opaque(nc);
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static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff,
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0xff, 0xff, 0xff};
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int unicast, broadcast, multicast;
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struct desc bd;
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ssize_t ret;
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unicast = ~buf[0] & 0x1;
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broadcast = memcmp(buf, sa_bcast, 6) == 0;
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multicast = !unicast && !broadcast;
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if (size < 12) {
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s->regs[DMA_STATUS] |= DMA_STATUS_RI | DMA_STATUS_NIS;
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ret = -1;
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goto out;
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}
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xgmac_read_desc(s, &bd, 1);
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if ((bd.ctl_stat & 0x80000000) == 0) {
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s->regs[DMA_STATUS] |= DMA_STATUS_RU | DMA_STATUS_AIS;
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ret = size;
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goto out;
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}
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cpu_physical_memory_write(bd.buffer1_addr, buf, size);
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/* Add in the 4 bytes for crc (the real hw returns length incl crc) */
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size += 4;
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bd.ctl_stat = (size << 16) | 0x300;
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xgmac_write_desc(s, &bd, 1);
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s->stats.rx_bytes += size;
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s->stats.rx++;
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if (multicast) {
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s->stats.rx_mcast++;
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} else if (broadcast) {
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s->stats.rx_bcast++;
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}
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s->regs[DMA_STATUS] |= DMA_STATUS_RI | DMA_STATUS_NIS;
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ret = size;
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out:
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enet_update_irq(s);
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return ret;
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}
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static void eth_cleanup(NetClientState *nc)
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{
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struct XgmacState *s = qemu_get_nic_opaque(nc);
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s->nic = NULL;
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}
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static NetClientInfo net_xgmac_enet_info = {
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.type = NET_CLIENT_OPTIONS_KIND_NIC,
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.size = sizeof(NICState),
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.can_receive = eth_can_rx,
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.receive = eth_rx,
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.cleanup = eth_cleanup,
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};
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static int xgmac_enet_init(SysBusDevice *dev)
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{
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struct XgmacState *s = FROM_SYSBUS(typeof(*s), dev);
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memory_region_init_io(&s->iomem, &enet_mem_ops, s, "xgmac", 0x1000);
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sysbus_init_mmio(dev, &s->iomem);
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sysbus_init_irq(dev, &s->sbd_irq);
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sysbus_init_irq(dev, &s->pmt_irq);
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sysbus_init_irq(dev, &s->mci_irq);
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qemu_macaddr_default_if_unset(&s->conf.macaddr);
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s->nic = qemu_new_nic(&net_xgmac_enet_info, &s->conf,
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object_get_typename(OBJECT(dev)), dev->qdev.id, s);
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qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
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s->regs[XGMAC_ADDR_HIGH(0)] = (s->conf.macaddr.a[5] << 8) |
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s->conf.macaddr.a[4];
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s->regs[XGMAC_ADDR_LOW(0)] = (s->conf.macaddr.a[3] << 24) |
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(s->conf.macaddr.a[2] << 16) |
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(s->conf.macaddr.a[1] << 8) |
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s->conf.macaddr.a[0];
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return 0;
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}
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static Property xgmac_properties[] = {
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DEFINE_NIC_PROPERTIES(struct XgmacState, conf),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void xgmac_enet_class_init(ObjectClass *klass, void *data)
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{
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SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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sbc->init = xgmac_enet_init;
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dc->vmsd = &vmstate_xgmac;
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dc->props = xgmac_properties;
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}
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static const TypeInfo xgmac_enet_info = {
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.name = "xgmac",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(struct XgmacState),
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.class_init = xgmac_enet_class_init,
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};
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static void xgmac_enet_register_types(void)
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{
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type_register_static(&xgmac_enet_info);
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}
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type_init(xgmac_enet_register_types)
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