120f738a46
This implements the Nested KVM HV hcall API for spapr under TCG. The L2 is switched in when the H_ENTER_NESTED hcall is made, and the L1 is switched back in returned from the hcall when a HV exception is sent to the vhyp. Register state is copied in and out according to the nested KVM HV hcall API specification. The hdecr timer is started when the L2 is switched in, and it provides the HDEC / 0x980 return to L1. The MMU re-uses the bare metal radix 2-level page table walker by using the get_pate method to point the MMU to the nested partition table entry. MMU faults due to partition scope errors raise HV exceptions and accordingly are routed back to the L1. The MMU does not tag translations for the L1 (direct) vs L2 (nested) guests, so the TLB is flushed on any L1<->L2 transition (hcall entry and exit). Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg: checkpatch fixes ] Message-Id: <20220216102545.1808018-10-npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
64 lines
1.8 KiB
C
64 lines
1.8 KiB
C
/*
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* sPAPR CPU core device.
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*
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* Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef HW_SPAPR_CPU_CORE_H
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#define HW_SPAPR_CPU_CORE_H
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#include "hw/cpu/core.h"
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#include "hw/qdev-core.h"
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#include "target/ppc/cpu-qom.h"
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#include "target/ppc/cpu.h"
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#include "qom/object.h"
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#define TYPE_SPAPR_CPU_CORE "spapr-cpu-core"
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OBJECT_DECLARE_TYPE(SpaprCpuCore, SpaprCpuCoreClass,
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SPAPR_CPU_CORE)
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#define SPAPR_CPU_CORE_TYPE_NAME(model) model "-" TYPE_SPAPR_CPU_CORE
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struct SpaprCpuCore {
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/*< private >*/
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CPUCore parent_obj;
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/*< public >*/
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PowerPCCPU **threads;
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int node_id;
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bool pre_3_0_migration; /* older machine don't know about SpaprCpuState */
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};
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struct SpaprCpuCoreClass {
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DeviceClass parent_class;
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const char *cpu_type;
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};
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const char *spapr_get_cpu_core_type(const char *cpu_type);
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void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip,
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target_ulong r1, target_ulong r3,
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target_ulong r4);
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typedef struct SpaprCpuState {
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uint64_t vpa_addr;
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uint64_t slb_shadow_addr, slb_shadow_size;
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uint64_t dtl_addr, dtl_size;
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bool prod; /* not migrated, only used to improve dispatch latencies */
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struct ICPState *icp;
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struct XiveTCTX *tctx;
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/* Fields for nested-HV support */
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bool in_nested; /* true while the L2 is executing */
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CPUPPCState *nested_host_state; /* holds the L1 state while L2 executes */
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int64_t nested_tb_offset; /* L1->L2 TB offset */
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} SpaprCpuState;
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static inline SpaprCpuState *spapr_cpu_state(PowerPCCPU *cpu)
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{
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return (SpaprCpuState *)cpu->machine_data;
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}
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#endif
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