Green Wan e22d90f5f9 hw/dma: sifive_pdma: allow non-multiple transaction size transactions ... Real PDMA is able to deal with non-multiple transaction size transactions. The following result is PDMA tested in U-Boot on Unmatched board: => mw.l 0x3000000 0x0 <= Disclaim channel 0 => mw.l 0x3000000 0x1 <= Claim channel 0 => mw.l 0x3000004 0x11000000 <= wsize = rsize = 1 (2^1 = 2 bytes) => mw.q 0x3000008 0x3 <= NextBytes = 3 => mw.q 0x3000010 0x84000000 <= NextDestination = 0x84000000 => mw.q 0x3000018 0x84001000 <= NextSource = 0x84001000 => mw.l 0x84000000 0x87654321 <= Fill test data to dst => mw.l 0x84001000 0x12345678 <= Fill test data to src => md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents 84000000: 87654321 !Ce. 84001000: 12345678 xV4. => md.l 0x3000000 8 <= Dump PDMA status 03000000: 00000001 11000000 00000003 00000000 ................ 03000010: 84000000 00000000 84001000 00000000 ................ => mw.l 0x3000000 0x3 <= Set channel 0 run and claim bits => md.l 0x3000000 8 <= Dump PDMA status 03000000: 40000001 11000000 00000003 00000000 ...@............ 03000010: 84000000 00000000 84001000 00000000 ................ => md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents 84000000: 87345678 xV4. 84001000: 12345678 xV4. Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Tested-by: Max Hsu <max.hsu@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210912130553.179501-4-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-09-21 07:56:49 +10:00
..
9pfs
acpi
adc
alpha
arm	hw/arm/mps2.c: Mark internal-only I2C buses as 'full'	2021-09-13 21:01:08 +01:00
audio
avr
block
char	hw/char: cadence_uart: Log a guest error when device is unclocked or in reset	2021-09-13 16:07:21 +01:00
core
cpu
cris
display	virtio-gpu: Add gl_flushed callback	2021-09-15 08:42:00 +02:00
dma	hw/dma: sifive_pdma: allow non-multiple transaction size transactions	2021-09-21 07:56:49 +10:00
gpio
hppa
hyperv
i2c
i386	intel_iommu: Fix typo in comments	2021-09-16 11:55:02 +02:00
ide
input	ps2: migration support for command reply queue	2021-09-10 07:32:32 +02:00
intc	hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT	2021-09-21 07:56:49 +10:00
ipack
ipmi
isa
m68k	mac_via: remove explicit viaN prefix from VIA IRQ gpios	2021-09-08 15:37:40 +02:00
mem
microblaze
mips
misc	hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase	2021-09-13 16:07:20 +01:00
net	virtio-net: fix use after unmap/free for sg	2021-09-17 16:07:52 +08:00
nios2
nubus
nvme
nvram	fw_cfg: add etc/msr_feature_control	2021-09-13 13:56:26 +02:00
openrisc
pci
pci-bridge
pci-host
pcmcia
ppc
rdma
remote
riscv	hw/riscv: virt: Add optional ACLINT support to virt machine	2021-09-21 07:56:49 +10:00
rtc
rx
s390x	s390x/cpumodel: Add more feature to gen16 default model	2021-09-07 13:36:43 +02:00
scsi
sd
sensor
sh4
smbios
sparc	sun4m: fix setting CPU id when more than one CPU is present	2021-09-08 11:09:45 +01:00
sparc64
ssi
timer	hw/timer: Add SiFive PWM support	2021-09-21 07:56:49 +10:00
tpm
tricore
usb
vfio	hw/vfio: Fix typo in comments	2021-09-16 11:57:01 +02:00
virtio
watchdog
xen
xenpv
xtensa
Kconfig
meson.build