55 lines
1.9 KiB
Diff
55 lines
1.9 KiB
Diff
switch MTRRs to cover only the PCI range and default to WB (Alex Williamson)
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This matches how some bare metal machines report MTRRs and avoids
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the problem of running out of MTRRs to cover all of RAM.
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Signed-off-by: Alex Williamson <alex.williamson@hp.com>
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Signed-off-by: Avi Kivity <avi@redhat.com>
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Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
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Index: bochs/bios/rombios32.c
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===================================================================
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--- bochs.orig/bios/rombios32.c
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+++ bochs/bios/rombios32.c
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@@ -525,7 +525,6 @@ void setup_mtrr(void)
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uint8_t valb[8];
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uint64_t val;
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} u;
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- uint64_t vbase, vmask;
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mtrr_cap = rdmsr(MSR_MTRRcap);
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vcnt = mtrr_cap & 0xff;
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@@ -552,25 +551,10 @@ void setup_mtrr(void)
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wrmsr_smp(MSR_MTRRfix4K_E8000, 0);
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wrmsr_smp(MSR_MTRRfix4K_F0000, 0);
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wrmsr_smp(MSR_MTRRfix4K_F8000, 0);
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- vbase = 0;
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- --vcnt; /* leave one mtrr for VRAM */
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- for (i = 0; i < vcnt && vbase < ram_size; ++i) {
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- vmask = (1ull << 40) - 1;
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- while (vbase + vmask + 1 > ram_size)
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- vmask >>= 1;
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- wrmsr_smp(MTRRphysBase_MSR(i), vbase | 6);
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- wrmsr_smp(MTRRphysMask_MSR(i), (~vmask & 0xfffffff000ull) | 0x800);
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- vbase += vmask + 1;
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- }
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- for (vbase = 1ull << 32; i < vcnt && vbase < ram_end; ++i) {
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- vmask = (1ull << 40) - 1;
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- while (vbase + vmask + 1 > ram_end)
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- vmask >>= 1;
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- wrmsr_smp(MTRRphysBase_MSR(i), vbase | 6);
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- wrmsr_smp(MTRRphysMask_MSR(i), (~vmask & 0xfffffff000ull) | 0x800);
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- vbase += vmask + 1;
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- }
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- wrmsr_smp(MSR_MTRRdefType, 0xc00);
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+ /* Mark 3.5-4GB as UC, anything not specified defaults to WB */
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+ wrmsr_smp(MTRRphysBase_MSR(0), 0xe0000000ull | 0);
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+ wrmsr_smp(MTRRphysMask_MSR(0), ~(0x20000000ull - 1) | 0x800);
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+ wrmsr_smp(MSR_MTRRdefType, 0xc06);
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}
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void ram_probe(void)
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