150 lines
4.6 KiB
C
150 lines
4.6 KiB
C
/*
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* Copyright (c) 2021 Alibek Omarov
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "exec/memory.h"
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#include "exec/address-spaces.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-properties-system.h"
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#include "hw/sysbus.h"
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#include "chardev/char-fe.h"
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#include "hw/char/lmscon.h"
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#include "trace.h"
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#define LMS_CONS_DATA_PORT 0x300UL /* On READ - data from keyboard */
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/* On WRITE - data to debug ouput */
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/* port (console/journal) */
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#define LMS_CONS_STATUS_PORT 0x301UL /* On READ - data available on 0x300 */
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/* On WRITE - shift count for 0x304 */
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#define LMS_NSOCK_BADDR_PORT 0x302UL /* On READ - network socket base addr*/
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/* On WRITE - the same. */
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#define LMS_NSOCK_DATA_PORT 0x303UL /* On READ - data from network socket*/
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/* On WRITE - data to network socket*/
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#define LMS_TRACE_CNTL_PORT 0x304UL /* On READ - state of the instruction*/
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/* counter */
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/* On WRITE - LMS tracer control */
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/* (1 - start, 0 - stop) */
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#define LMS_TRACE_CNTL_OFF 0
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#define LMS_TRACE_CNTL_ON 1
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static void lmscon_mem_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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LMSCONState *s = opaque;
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trace_lmscon_write(addr, val, size);
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if (!qemu_chr_fe_backend_connected(&s->chr))
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return;
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switch(LMS_CONS_DATA_PORT + addr)
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{
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case LMS_CONS_DATA_PORT:
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if (size == 1) {
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s->tx = val;
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qemu_chr_fe_write_all(&s->chr, (uint8_t*)&s->tx, size);
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} else {
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qemu_log_mask(LOG_UNIMP, "%s: LMS_CONS_DATA_PORT unknown size %d\n",
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__func__, size);
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}
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "%s: unimplemented lmscon packet %lx\n",
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__func__, LMS_CONS_DATA_PORT + addr);
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break;
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}
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}
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static uint64_t lmscon_mem_read(void *opaque, hwaddr addr, unsigned size)
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{
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LMSCONState *s = opaque;
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uint64_t r = 0;
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switch(LMS_CONS_DATA_PORT + addr)
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{
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case LMS_CONS_DATA_PORT:
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if (!qemu_chr_fe_backend_connected(&s->chr))
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r = 0xFFFFFFFF; /* port disabled */
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else qemu_chr_fe_read_all(&s->chr, (uint8_t*)&r, size);
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "%s: unimplemented lmscon packet %lx\n",
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__func__, LMS_CONS_DATA_PORT + addr);
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break;
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}
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trace_lmscon_read(addr, r, size);
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return r;
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}
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static const MemoryRegionOps lmscon_mem_ops = {
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.read = lmscon_mem_read,
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.write = lmscon_mem_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 4,
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},
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};
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static void lmscon_realize(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sb = SYS_BUS_DEVICE(dev);
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LMSCONState *s = LMSCON(dev);
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const uint64_t size = LMS_TRACE_CNTL_PORT - LMS_CONS_DATA_PORT + 1;
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memory_region_init_io(&s->io, OBJECT(dev), &lmscon_mem_ops, s, "lmscon", size);
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sysbus_add_io(sb, LMS_CONS_DATA_PORT, &s->io);
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sysbus_init_ioports(sb, LMS_CONS_DATA_PORT, size);
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}
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static Property lmscon_properties[] = {
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DEFINE_PROP_CHR("chr", LMSCONState, chr),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void lmscon_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = lmscon_realize;
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device_class_set_props(dc, lmscon_properties);
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set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
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}
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static TypeInfo lmscon_info = {
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.name = TYPE_LMSCON,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(LMSCONState),
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.class_init = lmscon_class_init
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};
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static void lmscon_register_types(void)
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{
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type_register_static(&lmscon_info);
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}
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type_init(lmscon_register_types)
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