cb3778a045
The e500 PCI controller has configurable windows that allow a guest OS to selectively map parts of the PCI bus space to CPU address space and to selectively map parts of the CPU address space for DMA requests into PCI visible address ranges. So far, we've simply assumed that this mapping is 1:1 and ignored it. However, the PCICSRBAR (CCSR mapped in PCI bus space) always has to live inside the first 32bits of address space. This means if we always treat all mappings as 1:1, this map will collide with our RAM map from the CPU's point of view. So this patch adds proper ATMU support which allows us to keep the PCICSRBAR below 32bits local to the PCI bus and have another, different window to PCI BARs at the upper end of address space. We leverage this on e500plat though, mpc8544ds stays virtually 1:1 like it was before, but now also goes via ATMU. With this patch, I can run guests with lots of RAM and not coincidently access MSI-X mappings while I really want to access RAM. Signed-off-by: Alexander Graf <agraf@suse.de>
74 lines
2.2 KiB
C
74 lines
2.2 KiB
C
/*
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* Generic device-tree-driven paravirt PPC e500 platform
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*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include "config.h"
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#include "qemu-common.h"
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#include "e500.h"
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#include "hw/boards.h"
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#include "sysemu/device_tree.h"
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#include "hw/pci/pci.h"
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#include "hw/ppc/openpic.h"
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#include "kvm_ppc.h"
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static void e500plat_fixup_devtree(PPCE500Params *params, void *fdt)
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{
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const char model[] = "QEMU ppce500";
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const char compatible[] = "fsl,qemu-e500";
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qemu_fdt_setprop(fdt, "/", "model", model, sizeof(model));
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qemu_fdt_setprop(fdt, "/", "compatible", compatible,
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sizeof(compatible));
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}
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static void e500plat_init(MachineState *machine)
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{
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PPCE500Params params = {
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.pci_first_slot = 0x1,
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.pci_nr_slots = PCI_SLOT_MAX - 1,
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.fixup_devtree = e500plat_fixup_devtree,
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.mpic_version = OPENPIC_MODEL_FSL_MPIC_42,
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.has_mpc8xxx_gpio = true,
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.has_platform_bus = true,
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.platform_bus_base = 0xf00000000ULL,
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.platform_bus_size = (128ULL * 1024 * 1024),
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.platform_bus_first_irq = 5,
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.platform_bus_num_irqs = 10,
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.ccsrbar_base = 0xFE0000000ULL,
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.pci_pio_base = 0xFE1000000ULL,
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.pci_mmio_base = 0xC00000000ULL,
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.pci_mmio_bus_base = 0xE0000000ULL,
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.spin_base = 0xFEF000000ULL,
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};
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/* Older KVM versions don't support EPR which breaks guests when we announce
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MPIC variants that support EPR. Revert to an older one for those */
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if (kvm_enabled() && !kvmppc_has_cap_epr()) {
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params.mpic_version = OPENPIC_MODEL_FSL_MPIC_20;
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}
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ppce500_init(machine, ¶ms);
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}
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static QEMUMachine e500plat_machine = {
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.name = "ppce500",
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.desc = "generic paravirt e500 platform",
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.init = e500plat_init,
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.max_cpus = 32,
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.has_dynamic_sysbus = true,
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};
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static void e500plat_machine_init(void)
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{
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qemu_register_machine(&e500plat_machine);
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}
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machine_init(e500plat_machine_init);
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