7993f8bc51
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1099 c046a42c-6fe2-441c-8c8c-71466251a162
98 lines
2.6 KiB
C
98 lines
2.6 KiB
C
/*
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* QEMU Sparc timer controller emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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/*
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* Registers of hardware timer in sun4m.
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*/
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struct sun4m_timer_percpu {
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volatile unsigned int l14_timer_limit; /* Initial value is 0x009c4000 */
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volatile unsigned int l14_cur_count;
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};
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struct sun4m_timer_global {
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volatile unsigned int l10_timer_limit;
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volatile unsigned int l10_cur_count;
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};
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typedef struct TIMERState {
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uint32_t addr;
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uint32_t timer_regs[2];
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int irq;
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} TIMERState;
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static uint32_t timer_mem_readl(void *opaque, target_phys_addr_t addr)
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{
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TIMERState *s = opaque;
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uint32_t saddr;
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saddr = (addr - s->addr) >> 2;
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switch (saddr) {
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default:
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return s->timer_regs[saddr];
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break;
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}
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return 0;
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}
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static void timer_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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TIMERState *s = opaque;
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uint32_t saddr;
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saddr = (addr - s->addr) >> 2;
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switch (saddr) {
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default:
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s->timer_regs[saddr] = val;
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break;
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}
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}
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static CPUReadMemoryFunc *timer_mem_read[3] = {
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timer_mem_readl,
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timer_mem_readl,
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timer_mem_readl,
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};
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static CPUWriteMemoryFunc *timer_mem_write[3] = {
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timer_mem_writel,
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timer_mem_writel,
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timer_mem_writel,
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};
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void timer_init(uint32_t addr, int irq)
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{
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int timer_io_memory;
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TIMERState *s;
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s = qemu_mallocz(sizeof(TIMERState));
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if (!s)
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return;
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s->addr = addr;
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s->irq = irq;
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timer_io_memory = cpu_register_io_memory(0, timer_mem_read, timer_mem_write, s);
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cpu_register_physical_memory(addr, 2, timer_io_memory);
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}
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