Xuzhou Cheng d6bafaf45c hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips ... Now that the Xilinx CSU DMA model is implemented, the existing DMA related dead codes in the ZynqMP QSPI are useless and should be removed. The maximum register number is also updated to only include the QSPI registers. Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com> Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20210303135254.3970-6-bmeng.cn@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2021-03-10 13:54:51 +00:00
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aspeed_smc.c
imx_spi.c
Kconfig	hw/ssi: Add SiFive SPI controller support	2021-03-04 09:43:29 -05:00
meson.build	hw/ssi: Add SiFive SPI controller support	2021-03-04 09:43:29 -05:00
mss-spi.c
npcm7xx_fiu.c
omap_spi.c
pl022.c
sifive_spi.c	hw/ssi: Add SiFive SPI controller support	2021-03-04 09:43:29 -05:00
ssi.c
stm32f2xx_spi.c
trace-events
trace.h
xilinx_spi.c
xilinx_spips.c	hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips	2021-03-10 13:54:51 +00:00