Alistair Francis e3fba4bab6 target/riscv: Add Hypervisor trap return support ... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>		2020-02-27 13:45:43 -08:00
..
insn_trans	target/riscv: fsd/fsw doesn't dirty FP state	2020-01-16 10:03:08 -08:00
cpu_bits.h	target/riscv: Add virtual register swapping function	2020-02-27 13:45:35 -08:00
cpu_helper.c	target/riscv: Add hypvervisor trap support	2020-02-27 13:45:42 -08:00
cpu_user.h
cpu-param.h
cpu.c	target/riscv: Dump Hypervisor registers if enabled	2020-02-27 13:45:31 -08:00
cpu.h	target/riscv: Add virtual register swapping function	2020-02-27 13:45:35 -08:00
csr.c	target/riscv: Extend the SIP CSR to support virtulisation	2020-02-27 13:45:38 -08:00
fpu_helper.c
gdbstub.c	target/riscv: Add the Hypervisor CSRs to CPUState	2020-02-27 13:45:25 -08:00
helper.h
insn16-32.decode
insn16-64.decode
insn16.decode
insn32-64.decode
insn32.decode
instmap.h	target/riscv: progressively load the instruction during decode	2020-02-25 20:20:23 +00:00
Makefile.objs
monitor.c
op_helper.c	target/riscv: Add Hypervisor trap return support	2020-02-27 13:45:43 -08:00
pmp.c	target/riscv: PMP violation due to wrong size parameter	2019-10-28 08:46:33 -07:00
pmp.h
trace-events
translate.c	target/riscv: Print priv and virt in disas log	2020-02-27 13:45:31 -08:00