afa4f6653d
There's a common pattern in QEMU where a function needs to perform a data load or store of an N byte integer in a particular endianness. At the moment this is handled by doing a switch() on the size and calling the appropriate ld*_p or st*_p function for each size. Provide a new family of functions ldn_*_p() and stn_*_p() which take the size as an argument and do the switch() themselves. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180611171007.4165-2-peter.maydell@linaro.org
412 lines
12 KiB
ReStructuredText
412 lines
12 KiB
ReStructuredText
..
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Copyright (c) 2017 Linaro Limited
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Written by Peter Maydell
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===================
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Load and Store APIs
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===================
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QEMU internally has multiple families of functions for performing
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loads and stores. This document attempts to enumerate them all
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and indicate when to use them. It does not provide detailed
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documentation of each API -- for that you should look at the
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documentation comments in the relevant header files.
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``ld*_p and st*_p``
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~~~~~~~~~~~~~~~~~~~
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These functions operate on a host pointer, and should be used
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when you already have a pointer into host memory (corresponding
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to guest ram or a local buffer). They deal with doing accesses
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with the desired endianness and with correctly handling
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potentially unaligned pointer values.
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Function names follow the pattern:
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load: ``ld{type}{sign}{size}_{endian}_p(ptr)``
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store: ``st{type}{size}_{endian}_p(ptr, val)``
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``type``
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- (empty) : integer access
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- ``f`` : float access
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``sign``
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- (empty) : for 32 or 64 bit sizes (including floats and doubles)
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- ``u`` : unsigned
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- ``s`` : signed
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``size``
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- ``b`` : 8 bits
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- ``w`` : 16 bits
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- ``l`` : 32 bits
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- ``q`` : 64 bits
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``endian``
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- ``he`` : host endian
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- ``be`` : big endian
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- ``le`` : little endian
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The ``_{endian}`` infix is omitted for target-endian accesses.
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The target endian accessors are only available to source
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files which are built per-target.
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There are also functions which take the size as an argument:
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load: ``ldn{endian}_p(ptr, sz)``
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which performs an unsigned load of ``sz`` bytes from ``ptr``
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as an ``{endian}`` order value and returns it in a uint64_t.
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store: ``stn{endian}_p(ptr, sz, val)``
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which stores ``val`` to ``ptr`` as an ``{endian}`` order value
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of size ``sz`` bytes.
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Regexes for git grep
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- ``\<ldf\?[us]\?[bwlq]\(_[hbl]e\)\?_p\>``
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- ``\<stf\?[bwlq]\(_[hbl]e\)\?_p\>``
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- ``\<ldn_\([hbl]e\)?_p\>``
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- ``\<stn_\([hbl]e\)?_p\>``
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``cpu_{ld,st}_*``
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~~~~~~~~~~~~~~~~~
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These functions operate on a guest virtual address. Be aware
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that these functions may cause a guest CPU exception to be
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taken (e.g. for an alignment fault or MMU fault) which will
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result in guest CPU state being updated and control longjumping
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out of the function call. They should therefore only be used
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in code that is implementing emulation of the target CPU.
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These functions may throw an exception (longjmp() back out
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to the top level TCG loop). This means they must only be used
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from helper functions where the translator has saved all
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necessary CPU state before generating the helper function call.
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It's usually better to use the ``_ra`` variants described below
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from helper functions, but these functions are the right choice
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for calls made from hooks like the CPU do_interrupt hook or
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when you know for certain that the translator had to save all
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the CPU state that ``cpu_restore_state()`` would restore anyway.
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Function names follow the pattern:
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load: ``cpu_ld{sign}{size}_{mmusuffix}(env, ptr)``
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store: ``cpu_st{size}_{mmusuffix}(env, ptr, val)``
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``sign``
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- (empty) : for 32 or 64 bit sizes
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- ``u`` : unsigned
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- ``s`` : signed
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``size``
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- ``b`` : 8 bits
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- ``w`` : 16 bits
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- ``l`` : 32 bits
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- ``q`` : 64 bits
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``mmusuffix`` is one of the generic suffixes ``data`` or ``code``, or
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(for softmmu configs) a target-specific MMU mode suffix as defined
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in the target's ``cpu.h``.
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Regexes for git grep
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- ``\<cpu_ld[us]\?[bwlq]_[a-zA-Z0-9]\+\>``
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- ``\<cpu_st[bwlq]_[a-zA-Z0-9]\+\>``
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``cpu_{ld,st}_*_ra``
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~~~~~~~~~~~~~~~~~~~~
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These functions work like the ``cpu_{ld,st}_*`` functions except
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that they also take a ``retaddr`` argument. This extra argument
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allows for correct unwinding of any exception that is taken,
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and should generally be the result of GETPC() called directly
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from the top level HELPER(foo) function (i.e. the return address
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in the generated code).
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These are generally the preferred way to do accesses by guest
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virtual address from helper functions; see the documentation
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of the non-``_ra`` variants for when those would be better.
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Calling these functions with a ``retaddr`` argument of 0 is
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equivalent to calling the non-``_ra`` version of the function.
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Function names follow the pattern:
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load: ``cpu_ld{sign}{size}_{mmusuffix}_ra(env, ptr, retaddr)``
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store: ``cpu_st{sign}{size}_{mmusuffix}_ra(env, ptr, val, retaddr)``
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Regexes for git grep
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- ``\<cpu_ld[us]\?[bwlq]_[a-zA-Z0-9]\+_ra\>``
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- ``\<cpu_st[bwlq]_[a-zA-Z0-9]\+_ra\>``
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``helper_*_{ld,st}*mmu``
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~~~~~~~~~~~~~~~~~~~~~~~~
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These functions are intended primarily to be called by the code
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generated by the TCG backend. They may also be called by target
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CPU helper function code. Like the ``cpu_{ld,st}_*_ra`` functions
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they perform accesses by guest virtual address; the difference is
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that these functions allow you to specify an ``opindex`` parameter
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which encodes (among other things) the mmu index to use for the
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access. This is necessary if your helper needs to make an access
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via a specific mmu index (for instance, an "always as non-privileged"
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access) rather than using the default mmu index for the current state
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of the guest CPU.
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The ``opindex`` parameter should be created by calling ``make_memop_idx()``.
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The ``retaddr`` parameter should be the result of GETPC() called directly
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from the top level HELPER(foo) function (or 0 if no guest CPU state
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unwinding is required).
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**TODO** The names of these functions are a bit odd for historical
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reasons because they were originally expected to be called only from
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within generated code. We should rename them to bring them
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more in line with the other memory access functions.
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load: ``helper_{endian}_ld{sign}{size}_mmu(env, addr, opindex, retaddr)``
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load (code): ``helper_{endian}_ld{sign}{size}_cmmu(env, addr, opindex, retaddr)``
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store: ``helper_{endian}_st{size}_mmu(env, addr, val, opindex, retaddr)``
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``sign``
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- (empty) : for 32 or 64 bit sizes
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- ``u`` : unsigned
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- ``s`` : signed
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``size``
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- ``b`` : 8 bits
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- ``w`` : 16 bits
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- ``l`` : 32 bits
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- ``q`` : 64 bits
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``endian``
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- ``le`` : little endian
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- ``be`` : big endian
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- ``ret`` : target endianness
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Regexes for git grep
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- ``\<helper_\(le\|be\|ret\)_ld[us]\?[bwlq]_c\?mmu\>``
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- ``\<helper_\(le\|be\|ret\)_st[bwlq]_mmu\>``
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``address_space_*``
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~~~~~~~~~~~~~~~~~~~
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These functions are the primary ones to use when emulating CPU
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or device memory accesses. They take an AddressSpace, which is the
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way QEMU defines the view of memory that a device or CPU has.
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(They generally correspond to being the "master" end of a hardware bus
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or bus fabric.)
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Each CPU has an AddressSpace. Some kinds of CPU have more than
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one AddressSpace (for instance ARM guest CPUs have an AddressSpace
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for the Secure world and one for NonSecure if they implement TrustZone).
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Devices which can do DMA-type operations should generally have an
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AddressSpace. There is also a "system address space" which typically
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has all the devices and memory that all CPUs can see. (Some older
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device models use the "system address space" rather than properly
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modelling that they have an AddressSpace of their own.)
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Functions are provided for doing byte-buffer reads and writes,
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and also for doing one-data-item loads and stores.
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In all cases the caller provides a MemTxAttrs to specify bus
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transaction attributes, and can check whether the memory transaction
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succeeded using a MemTxResult return code.
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``address_space_read(address_space, addr, attrs, buf, len)``
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``address_space_write(address_space, addr, attrs, buf, len)``
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``address_space_rw(address_space, addr, attrs, buf, len, is_write)``
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``address_space_ld{sign}{size}_{endian}(address_space, addr, attrs, txresult)``
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``address_space_st{size}_{endian}(address_space, addr, val, attrs, txresult)``
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``sign``
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- (empty) : for 32 or 64 bit sizes
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- ``u`` : unsigned
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(No signed load operations are provided.)
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``size``
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- ``b`` : 8 bits
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- ``w`` : 16 bits
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- ``l`` : 32 bits
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- ``q`` : 64 bits
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``endian``
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- ``le`` : little endian
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- ``be`` : big endian
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The ``_{endian}`` suffix is omitted for byte accesses.
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Regexes for git grep
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- ``\<address_space_\(read\|write\|rw\)\>``
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- ``\<address_space_ldu\?[bwql]\(_[lb]e\)\?\>``
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- ``\<address_space_st[bwql]\(_[lb]e\)\?\>``
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``{ld,st}*_phys``
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~~~~~~~~~~~~~~~~~
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These are functions which are identical to
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``address_space_{ld,st}*``, except that they always pass
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``MEMTXATTRS_UNSPECIFIED`` for the transaction attributes, and ignore
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whether the transaction succeeded or failed.
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The fact that they ignore whether the transaction succeeded means
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they should not be used in new code, unless you know for certain
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that your code will only be used in a context where the CPU or
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device doing the access has no way to report such an error.
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``load: ld{sign}{size}_{endian}_phys``
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``store: st{size}_{endian}_phys``
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``sign``
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- (empty) : for 32 or 64 bit sizes
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- ``u`` : unsigned
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(No signed load operations are provided.)
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``size``
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- ``b`` : 8 bits
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- ``w`` : 16 bits
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- ``l`` : 32 bits
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- ``q`` : 64 bits
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``endian``
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- ``le`` : little endian
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- ``be`` : big endian
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The ``_{endian}_`` infix is omitted for byte accesses.
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Regexes for git grep
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- ``\<ldu\?[bwlq]\(_[bl]e\)\?_phys\>``
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- ``\<st[bwlq]\(_[bl]e\)\?_phys\>``
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``cpu_physical_memory_*``
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~~~~~~~~~~~~~~~~~~~~~~~~~
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These are convenience functions which are identical to
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``address_space_*`` but operate specifically on the system address space,
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always pass a ``MEMTXATTRS_UNSPECIFIED`` set of memory attributes and
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ignore whether the memory transaction succeeded or failed.
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For new code they are better avoided:
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* there is likely to be behaviour you need to model correctly for a
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failed read or write operation
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* a device should usually perform operations on its own AddressSpace
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rather than using the system address space
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``cpu_physical_memory_read``
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``cpu_physical_memory_write``
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``cpu_physical_memory_rw``
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Regexes for git grep
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- ``\<cpu_physical_memory_\(read\|write\|rw\)\>``
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``cpu_physical_memory_write_rom``
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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This function performs a write by physical address like
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``address_space_write``, except that if the write is to a ROM then
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the ROM contents will be modified, even though a write by the guest
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CPU to the ROM would be ignored.
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Note that unlike ``cpu_physical_memory_write()`` this function takes
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an AddressSpace argument, but unlike ``address_space_write()`` this
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function does not take a ``MemTxAttrs`` or return a ``MemTxResult``.
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**TODO**: we should probably clean up this inconsistency and
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turn the function into ``address_space_write_rom`` with an API
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matching ``address_space_write``.
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``cpu_physical_memory_write_rom``
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``cpu_memory_rw_debug``
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~~~~~~~~~~~~~~~~~~~~~~~
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Access CPU memory by virtual address for debug purposes.
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This function is intended for use by the GDB stub and similar code.
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It takes a virtual address, converts it to a physical address via
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an MMU lookup using the current settings of the specified CPU,
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and then performs the access (using ``address_space_rw`` for
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reads or ``cpu_physical_memory_write_rom`` for writes).
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This means that if the access is a write to a ROM then this
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function will modify the contents (whereas a normal guest CPU access
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would ignore the write attempt).
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``cpu_memory_rw_debug``
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``dma_memory_*``
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~~~~~~~~~~~~~~~~
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These behave like ``address_space_*``, except that they perform a DMA
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barrier operation first.
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**TODO**: We should provide guidance on when you need the DMA
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barrier operation and when it's OK to use ``address_space_*``, and
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make sure our existing code is doing things correctly.
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``dma_memory_read``
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``dma_memory_write``
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``dma_memory_rw``
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Regexes for git grep
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- ``\<dma_memory_\(read\|write\|rw\)\>``
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``pci_dma_*`` and ``{ld,st}*_pci_dma``
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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These functions are specifically for PCI device models which need to
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perform accesses where the PCI device is a bus master. You pass them a
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``PCIDevice *`` and they will do ``dma_memory_*`` operations on the
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correct address space for that device.
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``pci_dma_read``
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``pci_dma_write``
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``pci_dma_rw``
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``load: ld{sign}{size}_{endian}_pci_dma``
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``store: st{size}_{endian}_pci_dma``
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``sign``
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- (empty) : for 32 or 64 bit sizes
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- ``u`` : unsigned
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(No signed load operations are provided.)
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``size``
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- ``b`` : 8 bits
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- ``w`` : 16 bits
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- ``l`` : 32 bits
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- ``q`` : 64 bits
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``endian``
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- ``le`` : little endian
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- ``be`` : big endian
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The ``_{endian}_`` infix is omitted for byte accesses.
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Regexes for git grep
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- ``\<pci_dma_\(read\|write\|rw\)\>``
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- ``\<ldu\?[bwlq]\(_[bl]e\)\?_pci_dma\>``
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- ``\<st[bwlq]\(_[bl]e\)\?_pci_dma\>``
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