qemu-e2k/target
Peter Maydell e494cd0a1a target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access
A few subcases of VLDR/VSTR sysreg succeed but do not perform a
memory access:
 * VSTR of VPR when unprivileged
 * VLDR to VPR when unprivileged
 * VLDR to FPCXT_NS when fpInactive

In these cases, even though we don't do the memory access we should
still update the base register and perform the stack limit check if
the insn's addressing mode specifies writeback.  Our implementation
failed to do this, because we handle these side-effects inside the
memory_to_fp_sysreg() and fp_sysreg_to_memory() callback functions,
which are only called if there's something to load or store.

Fix this by adding an extra argument to the callbacks which is set to
true to actually perform the access and false to only do side effects
like writeback, and calling the callback with do_access = false
for the three cases listed above.

This produces slightly suboptimal code for the case of a write
to FPCXT_NS when the FPU is inactive and the insn didn't have
side effects (ie no writeback, or via VMSR), in which case we'll
generate a conditional branch over an unconditional branch.
But this doesn't seem to be important enough to merit requiring
the callback to report back whether it generated any code or not.

Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210618141019.10671-5-peter.maydell@linaro.org
2021-06-21 16:49:37 +01:00
..
alpha hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
arm target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access 2021-06-21 16:49:37 +01:00
avr hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
cris hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
hexagon hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
hppa target/hppa: Remove unused 'memory.h' header 2021-06-05 21:23:14 +02:00
i386 x86 queue, 2021-06-18 2021-06-21 11:26:04 +01:00
m68k softfloat: Introduce Floatx80RoundPrec 2021-06-03 14:04:02 -07:00
microblaze hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
mips target/mips: Fix 'Uncoditional' typo 2021-06-05 21:28:54 +02:00
nios2 target/nios2: fix page-fit instruction count 2021-06-05 21:17:10 +02:00
openrisc hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
ppc target/ppc: fix single-step exception regression 2021-06-03 18:10:31 +10:00
riscv target/riscv: rvb: add b-ext version cpu option 2021-06-08 09:59:46 +10:00
rx hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
s390x docs: fix references to docs/devel/tracing.rst 2021-06-02 06:51:09 +02:00
sh4 hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
sparc docs: fix references to docs/devel/tracing.rst 2021-06-02 06:51:09 +02:00
tricore hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
xtensa hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
meson.build Drop the deprecated unicore32 target 2021-05-12 18:20:52 +02:00