492 lines
16 KiB
C
492 lines
16 KiB
C
/*
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* NVDIMM ACPI Implementation
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*
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* Copyright(C) 2015 Intel Corporation.
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*
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* Author:
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* Xiao Guangrong <guangrong.xiao@linux.intel.com>
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*
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* NFIT is defined in ACPI 6.0: 5.2.25 NVDIMM Firmware Interface Table (NFIT)
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* and the DSM specification can be found at:
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* http://pmem.io/documents/NVDIMM_DSM_Interface_Example.pdf
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*
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* Currently, it only supports PMEM Virtualization.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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#include "qemu/osdep.h"
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#include "hw/acpi/acpi.h"
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#include "hw/acpi/aml-build.h"
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#include "hw/mem/nvdimm.h"
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static int nvdimm_plugged_device_list(Object *obj, void *opaque)
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{
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GSList **list = opaque;
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if (object_dynamic_cast(obj, TYPE_NVDIMM)) {
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DeviceState *dev = DEVICE(obj);
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if (dev->realized) { /* only realized NVDIMMs matter */
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*list = g_slist_append(*list, DEVICE(obj));
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}
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}
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object_child_foreach(obj, nvdimm_plugged_device_list, opaque);
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return 0;
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}
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/*
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* inquire plugged NVDIMM devices and link them into the list which is
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* returned to the caller.
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*
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* Note: it is the caller's responsibility to free the list to avoid
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* memory leak.
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*/
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static GSList *nvdimm_get_plugged_device_list(void)
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{
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GSList *list = NULL;
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object_child_foreach(qdev_get_machine(), nvdimm_plugged_device_list,
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&list);
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return list;
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}
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#define NVDIMM_UUID_LE(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \
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{ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, \
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(b) & 0xff, ((b) >> 8) & 0xff, (c) & 0xff, ((c) >> 8) & 0xff, \
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(d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }
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/*
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* define Byte Addressable Persistent Memory (PM) Region according to
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* ACPI 6.0: 5.2.25.1 System Physical Address Range Structure.
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*/
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static const uint8_t nvdimm_nfit_spa_uuid[] =
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NVDIMM_UUID_LE(0x66f0d379, 0xb4f3, 0x4074, 0xac, 0x43, 0x0d, 0x33,
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0x18, 0xb7, 0x8c, 0xdb);
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/*
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* NVDIMM Firmware Interface Table
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* @signature: "NFIT"
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*
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* It provides information that allows OSPM to enumerate NVDIMM present in
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* the platform and associate system physical address ranges created by the
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* NVDIMMs.
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*
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* It is defined in ACPI 6.0: 5.2.25 NVDIMM Firmware Interface Table (NFIT)
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*/
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struct NvdimmNfitHeader {
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ACPI_TABLE_HEADER_DEF
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uint32_t reserved;
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} QEMU_PACKED;
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typedef struct NvdimmNfitHeader NvdimmNfitHeader;
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/*
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* define NFIT structures according to ACPI 6.0: 5.2.25 NVDIMM Firmware
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* Interface Table (NFIT).
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*/
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/*
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* System Physical Address Range Structure
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*
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* It describes the system physical address ranges occupied by NVDIMMs and
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* the types of the regions.
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*/
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struct NvdimmNfitSpa {
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uint16_t type;
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uint16_t length;
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uint16_t spa_index;
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uint16_t flags;
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uint32_t reserved;
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uint32_t proximity_domain;
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uint8_t type_guid[16];
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uint64_t spa_base;
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uint64_t spa_length;
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uint64_t mem_attr;
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} QEMU_PACKED;
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typedef struct NvdimmNfitSpa NvdimmNfitSpa;
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/*
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* Memory Device to System Physical Address Range Mapping Structure
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*
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* It enables identifying each NVDIMM region and the corresponding SPA
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* describing the memory interleave
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*/
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struct NvdimmNfitMemDev {
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uint16_t type;
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uint16_t length;
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uint32_t nfit_handle;
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uint16_t phys_id;
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uint16_t region_id;
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uint16_t spa_index;
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uint16_t dcr_index;
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uint64_t region_len;
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uint64_t region_offset;
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uint64_t region_dpa;
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uint16_t interleave_index;
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uint16_t interleave_ways;
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uint16_t flags;
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uint16_t reserved;
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} QEMU_PACKED;
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typedef struct NvdimmNfitMemDev NvdimmNfitMemDev;
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/*
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* NVDIMM Control Region Structure
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*
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* It describes the NVDIMM and if applicable, Block Control Window.
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*/
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struct NvdimmNfitControlRegion {
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uint16_t type;
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uint16_t length;
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uint16_t dcr_index;
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uint16_t vendor_id;
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uint16_t device_id;
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uint16_t revision_id;
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uint16_t sub_vendor_id;
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uint16_t sub_device_id;
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uint16_t sub_revision_id;
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uint8_t reserved[6];
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uint32_t serial_number;
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uint16_t fic;
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uint16_t num_bcw;
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uint64_t bcw_size;
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uint64_t cmd_offset;
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uint64_t cmd_size;
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uint64_t status_offset;
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uint64_t status_size;
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uint16_t flags;
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uint8_t reserved2[6];
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} QEMU_PACKED;
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typedef struct NvdimmNfitControlRegion NvdimmNfitControlRegion;
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/*
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* Module serial number is a unique number for each device. We use the
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* slot id of NVDIMM device to generate this number so that each device
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* associates with a different number.
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*
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* 0x123456 is a magic number we arbitrarily chose.
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*/
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static uint32_t nvdimm_slot_to_sn(int slot)
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{
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return 0x123456 + slot;
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}
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/*
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* handle is used to uniquely associate nfit_memdev structure with NVDIMM
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* ACPI device - nfit_memdev.nfit_handle matches with the value returned
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* by ACPI device _ADR method.
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*
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* We generate the handle with the slot id of NVDIMM device and reserve
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* 0 for NVDIMM root device.
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*/
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static uint32_t nvdimm_slot_to_handle(int slot)
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{
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return slot + 1;
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}
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/*
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* index uniquely identifies the structure, 0 is reserved which indicates
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* that the structure is not valid or the associated structure is not
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* present.
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*
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* Each NVDIMM device needs two indexes, one for nfit_spa and another for
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* nfit_dc which are generated by the slot id of NVDIMM device.
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*/
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static uint16_t nvdimm_slot_to_spa_index(int slot)
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{
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return (slot + 1) << 1;
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}
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/* See the comments of nvdimm_slot_to_spa_index(). */
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static uint32_t nvdimm_slot_to_dcr_index(int slot)
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{
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return nvdimm_slot_to_spa_index(slot) + 1;
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}
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/* ACPI 6.0: 5.2.25.1 System Physical Address Range Structure */
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static void
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nvdimm_build_structure_spa(GArray *structures, DeviceState *dev)
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{
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NvdimmNfitSpa *nfit_spa;
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uint64_t addr = object_property_get_int(OBJECT(dev), PC_DIMM_ADDR_PROP,
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NULL);
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uint64_t size = object_property_get_int(OBJECT(dev), PC_DIMM_SIZE_PROP,
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NULL);
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uint32_t node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP,
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NULL);
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int slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP,
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NULL);
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nfit_spa = acpi_data_push(structures, sizeof(*nfit_spa));
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nfit_spa->type = cpu_to_le16(0 /* System Physical Address Range
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Structure */);
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nfit_spa->length = cpu_to_le16(sizeof(*nfit_spa));
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nfit_spa->spa_index = cpu_to_le16(nvdimm_slot_to_spa_index(slot));
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/*
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* Control region is strict as all the device info, such as SN, index,
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* is associated with slot id.
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*/
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nfit_spa->flags = cpu_to_le16(1 /* Control region is strictly for
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management during hot add/online
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operation */ |
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2 /* Data in Proximity Domain field is
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valid*/);
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/* NUMA node. */
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nfit_spa->proximity_domain = cpu_to_le32(node);
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/* the region reported as PMEM. */
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memcpy(nfit_spa->type_guid, nvdimm_nfit_spa_uuid,
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sizeof(nvdimm_nfit_spa_uuid));
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nfit_spa->spa_base = cpu_to_le64(addr);
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nfit_spa->spa_length = cpu_to_le64(size);
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/* It is the PMEM and can be cached as writeback. */
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nfit_spa->mem_attr = cpu_to_le64(0x8ULL /* EFI_MEMORY_WB */ |
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0x8000ULL /* EFI_MEMORY_NV */);
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}
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/*
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* ACPI 6.0: 5.2.25.2 Memory Device to System Physical Address Range Mapping
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* Structure
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*/
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static void
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nvdimm_build_structure_memdev(GArray *structures, DeviceState *dev)
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{
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NvdimmNfitMemDev *nfit_memdev;
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uint64_t addr = object_property_get_int(OBJECT(dev), PC_DIMM_ADDR_PROP,
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NULL);
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uint64_t size = object_property_get_int(OBJECT(dev), PC_DIMM_SIZE_PROP,
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NULL);
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int slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP,
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NULL);
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uint32_t handle = nvdimm_slot_to_handle(slot);
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nfit_memdev = acpi_data_push(structures, sizeof(*nfit_memdev));
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nfit_memdev->type = cpu_to_le16(1 /* Memory Device to System Address
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Range Map Structure*/);
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nfit_memdev->length = cpu_to_le16(sizeof(*nfit_memdev));
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nfit_memdev->nfit_handle = cpu_to_le32(handle);
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/*
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* associate memory device with System Physical Address Range
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* Structure.
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*/
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nfit_memdev->spa_index = cpu_to_le16(nvdimm_slot_to_spa_index(slot));
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/* associate memory device with Control Region Structure. */
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nfit_memdev->dcr_index = cpu_to_le16(nvdimm_slot_to_dcr_index(slot));
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/* The memory region on the device. */
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nfit_memdev->region_len = cpu_to_le64(size);
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nfit_memdev->region_dpa = cpu_to_le64(addr);
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/* Only one interleave for PMEM. */
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nfit_memdev->interleave_ways = cpu_to_le16(1);
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}
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/*
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* ACPI 6.0: 5.2.25.5 NVDIMM Control Region Structure.
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*/
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static void nvdimm_build_structure_dcr(GArray *structures, DeviceState *dev)
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{
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NvdimmNfitControlRegion *nfit_dcr;
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int slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP,
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NULL);
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uint32_t sn = nvdimm_slot_to_sn(slot);
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nfit_dcr = acpi_data_push(structures, sizeof(*nfit_dcr));
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nfit_dcr->type = cpu_to_le16(4 /* NVDIMM Control Region Structure */);
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nfit_dcr->length = cpu_to_le16(sizeof(*nfit_dcr));
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nfit_dcr->dcr_index = cpu_to_le16(nvdimm_slot_to_dcr_index(slot));
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/* vendor: Intel. */
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nfit_dcr->vendor_id = cpu_to_le16(0x8086);
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nfit_dcr->device_id = cpu_to_le16(1);
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/* The _DSM method is following Intel's DSM specification. */
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nfit_dcr->revision_id = cpu_to_le16(1 /* Current Revision supported
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in ACPI 6.0 is 1. */);
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nfit_dcr->serial_number = cpu_to_le32(sn);
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nfit_dcr->fic = cpu_to_le16(0x201 /* Format Interface Code. See Chapter
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2: NVDIMM Device Specific Method
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(DSM) in DSM Spec Rev1.*/);
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}
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static GArray *nvdimm_build_device_structure(GSList *device_list)
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{
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GArray *structures = g_array_new(false, true /* clear */, 1);
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for (; device_list; device_list = device_list->next) {
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DeviceState *dev = device_list->data;
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/* build System Physical Address Range Structure. */
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nvdimm_build_structure_spa(structures, dev);
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/*
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* build Memory Device to System Physical Address Range Mapping
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* Structure.
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*/
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nvdimm_build_structure_memdev(structures, dev);
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/* build NVDIMM Control Region Structure. */
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nvdimm_build_structure_dcr(structures, dev);
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}
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return structures;
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}
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static void nvdimm_build_nfit(GSList *device_list, GArray *table_offsets,
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GArray *table_data, GArray *linker)
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{
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GArray *structures = nvdimm_build_device_structure(device_list);
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unsigned int header;
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acpi_add_table(table_offsets, table_data);
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/* NFIT header. */
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header = table_data->len;
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acpi_data_push(table_data, sizeof(NvdimmNfitHeader));
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/* NVDIMM device structures. */
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g_array_append_vals(table_data, structures->data, structures->len);
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build_header(linker, table_data,
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(void *)(table_data->data + header), "NFIT",
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sizeof(NvdimmNfitHeader) + structures->len, 1, NULL);
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g_array_free(structures, true);
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}
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#define NVDIMM_COMMON_DSM "NCAL"
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static void nvdimm_build_common_dsm(Aml *dev)
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{
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Aml *method, *ifctx, *function;
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uint8_t byte_list[1];
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method = aml_method(NVDIMM_COMMON_DSM, 4, AML_NOTSERIALIZED);
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function = aml_arg(2);
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/*
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* function 0 is called to inquire what functions are supported by
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* OSPM
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*/
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ifctx = aml_if(aml_equal(function, aml_int(0)));
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byte_list[0] = 0 /* No function Supported */;
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aml_append(ifctx, aml_return(aml_buffer(1, byte_list)));
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aml_append(method, ifctx);
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/* No function is supported yet. */
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byte_list[0] = 1 /* Not Supported */;
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aml_append(method, aml_return(aml_buffer(1, byte_list)));
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aml_append(dev, method);
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}
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static void nvdimm_build_device_dsm(Aml *dev)
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{
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Aml *method;
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method = aml_method("_DSM", 4, AML_NOTSERIALIZED);
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aml_append(method, aml_return(aml_call4(NVDIMM_COMMON_DSM, aml_arg(0),
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aml_arg(1), aml_arg(2), aml_arg(3))));
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aml_append(dev, method);
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}
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static void nvdimm_build_nvdimm_devices(GSList *device_list, Aml *root_dev)
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{
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for (; device_list; device_list = device_list->next) {
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DeviceState *dev = device_list->data;
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int slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP,
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NULL);
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uint32_t handle = nvdimm_slot_to_handle(slot);
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Aml *nvdimm_dev;
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nvdimm_dev = aml_device("NV%02X", slot);
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/*
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* ACPI 6.0: 9.20 NVDIMM Devices:
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*
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* _ADR object that is used to supply OSPM with unique address
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* of the NVDIMM device. This is done by returning the NFIT Device
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* handle that is used to identify the associated entries in ACPI
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* table NFIT or _FIT.
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*/
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aml_append(nvdimm_dev, aml_name_decl("_ADR", aml_int(handle)));
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nvdimm_build_device_dsm(nvdimm_dev);
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aml_append(root_dev, nvdimm_dev);
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}
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}
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static void nvdimm_build_ssdt(GSList *device_list, GArray *table_offsets,
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GArray *table_data, GArray *linker)
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{
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Aml *ssdt, *sb_scope, *dev;
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acpi_add_table(table_offsets, table_data);
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ssdt = init_aml_allocator();
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acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader));
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sb_scope = aml_scope("\\_SB");
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dev = aml_device("NVDR");
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/*
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* ACPI 6.0: 9.20 NVDIMM Devices:
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*
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* The ACPI Name Space device uses _HID of ACPI0012 to identify the root
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* NVDIMM interface device. Platform firmware is required to contain one
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* such device in _SB scope if NVDIMMs support is exposed by platform to
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* OSPM.
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* For each NVDIMM present or intended to be supported by platform,
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* platform firmware also exposes an ACPI Namespace Device under the
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* root device.
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*/
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aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0012")));
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nvdimm_build_common_dsm(dev);
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nvdimm_build_device_dsm(dev);
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nvdimm_build_nvdimm_devices(device_list, dev);
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aml_append(sb_scope, dev);
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aml_append(ssdt, sb_scope);
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/* copy AML table into ACPI tables blob and patch header there */
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g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len);
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build_header(linker, table_data,
|
|
(void *)(table_data->data + table_data->len - ssdt->buf->len),
|
|
"SSDT", ssdt->buf->len, 1, "NVDIMM");
|
|
free_aml_allocator();
|
|
}
|
|
|
|
void nvdimm_build_acpi(GArray *table_offsets, GArray *table_data,
|
|
GArray *linker)
|
|
{
|
|
GSList *device_list;
|
|
|
|
/* no NVDIMM device is plugged. */
|
|
device_list = nvdimm_get_plugged_device_list();
|
|
if (!device_list) {
|
|
return;
|
|
}
|
|
nvdimm_build_nfit(device_list, table_offsets, table_data, linker);
|
|
nvdimm_build_ssdt(device_list, table_offsets, table_data, linker);
|
|
g_slist_free(device_list);
|
|
}
|