Peter Maydell 21c2dd77a6 Revert "target/arm: Make number of counters in PMCR follow the CPU" ... This reverts commit f7fb73b8cd. This change turned out to be a bit half-baked, and doesn't work with KVM, which fails with the error: "qemu-system-aarch64: Failed to retrieve host CPU features" because KVM does not allow accessing of the PMCR_EL0 value in the scratch "query CPU ID registers" VM unless we have first set the KVM_ARM_VCPU_PMU_V3 feature on the VM. Revert the change for 6.0. Reported-by: Zenghui Yu <yuzenghui@huawei.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Zenghui Yu <yuzenghui@huawei.com> Message-id: 20210331154822.23332-1-peter.maydell@linaro.org		2021-04-06 11:49:14 +01:00
..
a32-uncond.decode
a32.decode
arch_dump.c
arm_ldst.h
arm-powerctl.c
arm-powerctl.h
cpu64.c	Revert "target/arm: Make number of counters in PMCR follow the CPU"	2021-04-06 11:49:14 +01:00
cpu_tcg.c	Revert "target/arm: Make number of counters in PMCR follow the CPU"	2021-04-06 11:49:14 +01:00
cpu-param.h	linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE	2021-02-16 13:06:16 +00:00
cpu-qom.h
cpu.c	target/arm: Make M-profile VTOR loads on reset handle memory aliasing	2021-03-23 11:47:31 +00:00
cpu.h	Revert "target/arm: Make number of counters in PMCR follow the CPU"	2021-04-06 11:49:14 +01:00
crypto_helper.c
debug_helper.c
gdbstub64.c
gdbstub.c	target/arm: use official org.gnu.gdb.aarch64.sve layout for registers	2021-01-18 10:05:06 +00:00
helper-a64.c	target/arm: Speed up aarch64 TBL/TBX	2021-03-05 15:17:34 +00:00
helper-a64.h	target/arm: Speed up aarch64 TBL/TBX	2021-03-05 15:17:34 +00:00
helper-sve.h
helper.c	Revert "target/arm: Make number of counters in PMCR follow the CPU"	2021-04-06 11:49:14 +01:00
helper.h
idau.h
internals.h	target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe	2021-03-05 15:17:34 +00:00
iwmmxt_helper.c
kvm64.c	Revert "target/arm: Make number of counters in PMCR follow the CPU"	2021-04-06 11:49:14 +01:00
kvm_arm.h	hw/arm/virt: KVM: The IPA lower bound is 32	2021-03-12 12:47:11 +00:00
kvm-consts.h
kvm-stub.c
kvm.c	hw/arm/virt: KVM: The IPA lower bound is 32	2021-03-12 12:47:11 +00:00
m_helper.c	semihosting: Move include/hw/semihosting/ -> include/semihosting/	2021-03-10 15:34:12 +00:00
m-nocp.decode
machine.c	target/arm: Don't migrate CPUARMState.features	2021-02-11 11:50:13 +00:00
meson.build	semihosting: Move ARM semihosting code to shared directories	2021-01-18 10:05:06 +00:00
monitor.c	target/arm: Add cpu properties to control pauth	2021-01-19 14:38:51 +00:00
mte_helper.c	target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks	2021-03-05 15:17:35 +00:00
neon_helper.c
neon-dp.decode
neon-ls.decode
neon-shared.decode
op_addsub.h
op_helper.c	target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate	2021-02-11 11:50:14 +00:00
pauth_helper.c	target/arm: Implement an IMPDEF pauth algorithm	2021-01-19 14:38:51 +00:00
psci.c
sve_helper.c	target/arm: Update sve reduction vs simd_desc	2021-03-12 12:40:10 +00:00
sve.decode
syndrome.h	target/arm: Split out syndrome.h from internals.h	2021-02-16 13:16:18 +00:00
t16.decode
t32.decode
tlb_helper.c	target/arm: Set ARMMMUFaultInfo.level in user-only arm_cpu_tlb_fill	2021-03-23 14:07:55 +00:00
trace-events
trace.h
translate-a64.c	semihosting: Move include/hw/semihosting/ -> include/semihosting/	2021-03-10 15:34:12 +00:00
translate-a64.h
translate-neon.c.inc
translate-sve.c	target/arm: Update sve reduction vs simd_desc	2021-03-12 12:40:10 +00:00
translate-vfp.c.inc	target/arm: Implement FPCXT_NS fp system register	2021-01-08 15:13:38 +00:00
translate.c	semihosting: Move include/hw/semihosting/ -> include/semihosting/	2021-03-10 15:34:12 +00:00
translate.h
vec_helper.c	target/arm: Speed up aarch64 TBL/TBX	2021-03-05 15:17:34 +00:00
vec_internal.h
vfp_helper.c
vfp-uncond.decode
vfp.decode