575bafd1f3
The BH will be scheduled when etsec->rx_buffer_len is becoming 0, which is the condition of queuing. Signed-off-by: Fam Zheng <famz@redhat.com> Reviewed-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1436955553-22791-7-git-send-email-famz@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
177 lines
5.5 KiB
C
177 lines
5.5 KiB
C
/*
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* QEMU Freescale eTSEC Emulator
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*
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* Copyright (c) 2011-2013 AdaCore
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef _ETSEC_H_
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#define _ETSEC_H_
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#include "hw/qdev.h"
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#include "hw/sysbus.h"
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#include "net/net.h"
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#include "hw/ptimer.h"
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/* Buffer Descriptors */
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typedef struct eTSEC_rxtx_bd {
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uint16_t flags;
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uint16_t length;
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uint32_t bufptr;
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} eTSEC_rxtx_bd;
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#define BD_WRAP (1 << 13)
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#define BD_INTERRUPT (1 << 12)
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#define BD_LAST (1 << 11)
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#define BD_TX_READY (1 << 15)
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#define BD_TX_PADCRC (1 << 14)
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#define BD_TX_TC (1 << 10)
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#define BD_TX_PREDEF (1 << 9)
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#define BD_TX_HFELC (1 << 7)
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#define BD_TX_CFRL (1 << 6)
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#define BD_TX_RC_MASK 0xF
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#define BD_TX_RC_OFFSET 0x2
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#define BD_TX_TOEUN (1 << 1)
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#define BD_TX_TR (1 << 0)
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#define BD_RX_EMPTY (1 << 15)
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#define BD_RX_RO1 (1 << 14)
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#define BD_RX_FIRST (1 << 10)
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#define BD_RX_MISS (1 << 8)
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#define BD_RX_BROADCAST (1 << 7)
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#define BD_RX_MULTICAST (1 << 6)
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#define BD_RX_LG (1 << 5)
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#define BD_RX_NO (1 << 4)
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#define BD_RX_SH (1 << 3)
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#define BD_RX_CR (1 << 2)
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#define BD_RX_OV (1 << 1)
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#define BD_RX_TR (1 << 0)
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/* Tx FCB flags */
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#define FCB_TX_VLN (1 << 7)
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#define FCB_TX_IP (1 << 6)
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#define FCB_TX_IP6 (1 << 5)
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#define FCB_TX_TUP (1 << 4)
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#define FCB_TX_UDP (1 << 3)
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#define FCB_TX_CIP (1 << 2)
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#define FCB_TX_CTU (1 << 1)
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#define FCB_TX_NPH (1 << 0)
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/* PHY Status Register */
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#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
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#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
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#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
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#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
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#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
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#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
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#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
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#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
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#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
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#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
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#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
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#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
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#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
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#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
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#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
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/* eTSEC */
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/* Number of register in the device */
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#define ETSEC_REG_NUMBER 1024
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typedef struct eTSEC_Register {
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const char *name;
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const char *desc;
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uint32_t access;
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uint32_t value;
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} eTSEC_Register;
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typedef struct eTSEC {
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SysBusDevice busdev;
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MemoryRegion io_area;
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eTSEC_Register regs[ETSEC_REG_NUMBER];
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NICState *nic;
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NICConf conf;
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/* Tx */
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uint8_t *tx_buffer;
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uint32_t tx_buffer_len;
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eTSEC_rxtx_bd first_bd;
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/* Rx */
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uint8_t *rx_buffer;
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uint32_t rx_buffer_len;
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uint32_t rx_remaining_data;
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uint8_t rx_first_in_frame;
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uint8_t rx_fcb_size;
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eTSEC_rxtx_bd rx_first_bd;
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uint8_t rx_fcb[10];
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uint32_t rx_padding;
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/* IRQs */
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qemu_irq tx_irq;
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qemu_irq rx_irq;
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qemu_irq err_irq;
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uint16_t phy_status;
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uint16_t phy_control;
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/* Polling */
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QEMUBH *bh;
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struct ptimer_state *ptimer;
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/* Whether we should flush the rx queue when buffer becomes available. */
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bool need_flush;
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} eTSEC;
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#define TYPE_ETSEC_COMMON "eTSEC"
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#define ETSEC_COMMON(obj) \
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OBJECT_CHECK(eTSEC, (obj), TYPE_ETSEC_COMMON)
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#define eTSEC_TRANSMIT 1
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#define eTSEC_RECEIVE 2
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DeviceState *etsec_create(hwaddr base,
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MemoryRegion *mr,
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NICInfo *nd,
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qemu_irq tx_irq,
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qemu_irq rx_irq,
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qemu_irq err_irq);
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void etsec_walk_tx_ring(eTSEC *etsec, int ring_nbr);
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void etsec_walk_rx_ring(eTSEC *etsec, int ring_nbr);
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ssize_t etsec_rx_ring_write(eTSEC *etsec, const uint8_t *buf, size_t size);
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void etsec_write_miim(eTSEC *etsec,
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eTSEC_Register *reg,
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uint32_t reg_index,
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uint32_t value);
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void etsec_miim_link_status(eTSEC *etsec, NetClientState *nc);
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#endif /* ! _ETSEC_H_ */
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