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Yongbok Kim 01bc435b44 target-mips: implement R6 multi-threading 
MIPS Release 6 provides multi-threading features which replace
pre-R6 MT Module. CP0.Config3.MT is always 0 in R6, instead there is new
CP0.Config5.VP (Virtual Processor) bit which indicates presence of
multi-threading support which includes CP0.GlobalNumber register and
DVP/EVP instructions.

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-02-26 08:59:17 +00:00
..
libvixl libvixl: Avoid std::abs() of 64-bit type 2016-02-03 13:46:34 +00:00
alpha.c alpha: Clean up includes 2016-01-29 15:07:23 +00:00
arm-a64.cc disas/arm-a64.cc: Include osdep.h first 2016-02-23 12:43:04 +00:00
arm.c arm: Clean up includes 2016-01-29 15:07:23 +00:00
cris.c cris: Clean up includes 2016-01-29 15:07:24 +00:00
hppa.c disas: Clean up includes 2016-02-04 17:41:30 +00:00
i386.c disas: Clean up includes 2016-02-04 17:41:30 +00:00
ia64.c disas: Clean up includes 2016-02-04 17:41:30 +00:00
lm32.c
m68k.c disas: Clean up includes 2016-02-04 17:41:30 +00:00
Makefile.objs
microblaze.c
mips.c target-mips: implement R6 multi-threading 2016-02-26 08:59:17 +00:00
moxie.c moxie: Clean up includes 2016-01-29 15:07:25 +00:00
ppc.c ppc: Clean up includes 2016-01-29 15:07:22 +00:00
s390.c disas: Clean up includes 2016-02-04 17:41:30 +00:00
sh4.c sh4: Clean up includes 2016-01-29 15:07:24 +00:00
sparc.c disas: Clean up includes 2016-02-04 17:41:30 +00:00
tci.c disas: Clean up includes 2016-02-04 17:41:30 +00:00