596 lines
18 KiB
C
596 lines
18 KiB
C
/*
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* QEMU model of the Xilinx Zynq SPI controller
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*
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* Copyright (c) 2012 Peter A. G. Crosthwaite
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/sysbus.h"
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#include "sysemu/sysemu.h"
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#include "hw/ptimer.h"
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#include "qemu/log.h"
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#include "qemu/fifo8.h"
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#include "hw/ssi.h"
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#include "qemu/bitops.h"
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#ifdef XILINX_SPIPS_ERR_DEBUG
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#define DB_PRINT(...) do { \
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fprintf(stderr, ": %s: ", __func__); \
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fprintf(stderr, ## __VA_ARGS__); \
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} while (0);
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#else
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#define DB_PRINT(...)
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#endif
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/* config register */
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#define R_CONFIG (0x00 / 4)
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#define IFMODE (1 << 31)
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#define ENDIAN (1 << 26)
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#define MODEFAIL_GEN_EN (1 << 17)
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#define MAN_START_COM (1 << 16)
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#define MAN_START_EN (1 << 15)
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#define MANUAL_CS (1 << 14)
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#define CS (0xF << 10)
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#define CS_SHIFT (10)
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#define PERI_SEL (1 << 9)
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#define REF_CLK (1 << 8)
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#define FIFO_WIDTH (3 << 6)
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#define BAUD_RATE_DIV (7 << 3)
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#define CLK_PH (1 << 2)
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#define CLK_POL (1 << 1)
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#define MODE_SEL (1 << 0)
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/* interrupt mechanism */
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#define R_INTR_STATUS (0x04 / 4)
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#define R_INTR_EN (0x08 / 4)
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#define R_INTR_DIS (0x0C / 4)
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#define R_INTR_MASK (0x10 / 4)
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#define IXR_TX_FIFO_UNDERFLOW (1 << 6)
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#define IXR_RX_FIFO_FULL (1 << 5)
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#define IXR_RX_FIFO_NOT_EMPTY (1 << 4)
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#define IXR_TX_FIFO_FULL (1 << 3)
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#define IXR_TX_FIFO_NOT_FULL (1 << 2)
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#define IXR_TX_FIFO_MODE_FAIL (1 << 1)
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#define IXR_RX_FIFO_OVERFLOW (1 << 0)
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#define IXR_ALL ((IXR_TX_FIFO_UNDERFLOW<<1)-1)
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#define R_EN (0x14 / 4)
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#define R_DELAY (0x18 / 4)
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#define R_TX_DATA (0x1C / 4)
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#define R_RX_DATA (0x20 / 4)
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#define R_SLAVE_IDLE_COUNT (0x24 / 4)
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#define R_TX_THRES (0x28 / 4)
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#define R_RX_THRES (0x2C / 4)
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#define R_TXD1 (0x80 / 4)
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#define R_TXD2 (0x84 / 4)
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#define R_TXD3 (0x88 / 4)
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#define R_LQSPI_CFG (0xa0 / 4)
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#define R_LQSPI_CFG_RESET 0x03A002EB
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#define LQSPI_CFG_LQ_MODE (1 << 31)
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#define LQSPI_CFG_TWO_MEM (1 << 30)
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#define LQSPI_CFG_SEP_BUS (1 << 30)
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#define LQSPI_CFG_U_PAGE (1 << 28)
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#define LQSPI_CFG_MODE_EN (1 << 25)
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#define LQSPI_CFG_MODE_WIDTH 8
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#define LQSPI_CFG_MODE_SHIFT 16
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#define LQSPI_CFG_DUMMY_WIDTH 3
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#define LQSPI_CFG_DUMMY_SHIFT 8
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#define LQSPI_CFG_INST_CODE 0xFF
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#define R_LQSPI_STS (0xA4 / 4)
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#define LQSPI_STS_WR_RECVD (1 << 1)
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#define R_MOD_ID (0xFC / 4)
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#define R_MAX (R_MOD_ID+1)
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/* size of TXRX FIFOs */
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#define RXFF_A 32
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#define TXFF_A 32
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/* 16MB per linear region */
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#define LQSPI_ADDRESS_BITS 24
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/* Bite off 4k chunks at a time */
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#define LQSPI_CACHE_SIZE 1024
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#define SNOOP_CHECKING 0xFF
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#define SNOOP_NONE 0xFE
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#define SNOOP_STRIPING 0
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typedef enum {
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READ = 0x3,
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FAST_READ = 0xb,
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DOR = 0x3b,
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QOR = 0x6b,
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DIOR = 0xbb,
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QIOR = 0xeb,
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PP = 0x2,
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DPP = 0xa2,
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QPP = 0x32,
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} FlashCMD;
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typedef struct {
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SysBusDevice busdev;
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MemoryRegion iomem;
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MemoryRegion mmlqspi;
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qemu_irq irq;
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int irqline;
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uint8_t num_cs;
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uint8_t num_busses;
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uint8_t snoop_state;
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qemu_irq *cs_lines;
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SSIBus **spi;
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Fifo8 rx_fifo;
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Fifo8 tx_fifo;
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uint8_t num_txrx_bytes;
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uint32_t regs[R_MAX];
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uint32_t lqspi_buf[LQSPI_CACHE_SIZE];
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hwaddr lqspi_cached_addr;
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} XilinxSPIPS;
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#define TYPE_XILINX_SPIPS "xilinx,spips"
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#define XILINX_SPIPS(obj) \
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OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS)
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static inline int num_effective_busses(XilinxSPIPS *s)
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{
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return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS &&
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s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1;
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}
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static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
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{
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int i, j;
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bool found = false;
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int field = s->regs[R_CONFIG] >> CS_SHIFT;
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for (i = 0; i < s->num_cs; i++) {
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for (j = 0; j < num_effective_busses(s); j++) {
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int upage = !!(s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE);
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int cs_to_set = (j * s->num_cs + i + upage) %
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(s->num_cs * s->num_busses);
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if (~field & (1 << i) && !found) {
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DB_PRINT("selecting slave %d\n", i);
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qemu_set_irq(s->cs_lines[cs_to_set], 0);
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} else {
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qemu_set_irq(s->cs_lines[cs_to_set], 1);
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}
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}
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if (~field & (1 << i)) {
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found = true;
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}
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}
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if (!found) {
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s->snoop_state = SNOOP_CHECKING;
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}
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}
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static void xilinx_spips_update_ixr(XilinxSPIPS *s)
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{
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/* These are set/cleared as they occur */
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s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW |
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IXR_TX_FIFO_MODE_FAIL);
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/* these are pure functions of fifo state, set them here */
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s->regs[R_INTR_STATUS] |=
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(fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) |
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(s->rx_fifo.num >= s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY : 0) |
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(fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) |
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(s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0);
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/* drive external interrupt pin */
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int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] &
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IXR_ALL);
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if (new_irqline != s->irqline) {
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s->irqline = new_irqline;
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qemu_set_irq(s->irq, s->irqline);
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}
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}
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static void xilinx_spips_reset(DeviceState *d)
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{
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XilinxSPIPS *s = XILINX_SPIPS(d);
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int i;
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for (i = 0; i < R_MAX; i++) {
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s->regs[i] = 0;
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}
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fifo8_reset(&s->rx_fifo);
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fifo8_reset(&s->rx_fifo);
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/* non zero resets */
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s->regs[R_CONFIG] |= MODEFAIL_GEN_EN;
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s->regs[R_SLAVE_IDLE_COUNT] = 0xFF;
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s->regs[R_TX_THRES] = 1;
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s->regs[R_RX_THRES] = 1;
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/* FIXME: move magic number definition somewhere sensible */
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s->regs[R_MOD_ID] = 0x01090106;
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s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET;
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s->snoop_state = SNOOP_CHECKING;
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xilinx_spips_update_ixr(s);
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xilinx_spips_update_cs_lines(s);
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}
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static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
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{
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for (;;) {
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int i;
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uint8_t rx;
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uint8_t tx = 0;
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for (i = 0; i < num_effective_busses(s); ++i) {
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if (!i || s->snoop_state == SNOOP_STRIPING) {
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if (fifo8_is_empty(&s->tx_fifo)) {
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s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
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xilinx_spips_update_ixr(s);
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return;
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} else {
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tx = fifo8_pop(&s->tx_fifo);
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}
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}
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rx = ssi_transfer(s->spi[i], (uint32_t)tx);
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DB_PRINT("tx = %02x rx = %02x\n", tx, rx);
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if (!i || s->snoop_state == SNOOP_STRIPING) {
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if (fifo8_is_full(&s->rx_fifo)) {
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s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW;
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DB_PRINT("rx FIFO overflow");
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} else {
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fifo8_push(&s->rx_fifo, (uint8_t)rx);
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}
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}
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}
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switch (s->snoop_state) {
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case (SNOOP_CHECKING):
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switch (tx) { /* new instruction code */
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case READ: /* 3 address bytes, no dummy bytes/cycles */
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case PP:
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case DPP:
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case QPP:
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s->snoop_state = 3;
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break;
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case FAST_READ: /* 3 address bytes, 1 dummy byte */
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case DOR:
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case QOR:
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case DIOR: /* FIXME: these vary between vendor - set to spansion */
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s->snoop_state = 4;
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break;
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case QIOR: /* 3 address bytes, 2 dummy bytes */
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s->snoop_state = 6;
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break;
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default:
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s->snoop_state = SNOOP_NONE;
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}
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break;
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case (SNOOP_STRIPING):
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case (SNOOP_NONE):
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break;
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default:
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s->snoop_state--;
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}
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}
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}
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static inline void rx_data_bytes(XilinxSPIPS *s, uint32_t *value, int max)
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{
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int i;
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*value = 0;
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for (i = 0; i < max && !fifo8_is_empty(&s->rx_fifo); ++i) {
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uint32_t next = fifo8_pop(&s->rx_fifo) & 0xFF;
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*value |= next << 8 * (s->regs[R_CONFIG] & ENDIAN ? 3-i : i);
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}
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}
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static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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XilinxSPIPS *s = opaque;
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uint32_t mask = ~0;
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uint32_t ret;
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addr >>= 2;
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switch (addr) {
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case R_CONFIG:
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mask = 0x0002FFFF;
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break;
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case R_INTR_STATUS:
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case R_INTR_MASK:
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mask = IXR_ALL;
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break;
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case R_EN:
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mask = 0x1;
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break;
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case R_SLAVE_IDLE_COUNT:
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mask = 0xFF;
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break;
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case R_MOD_ID:
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mask = 0x01FFFFFF;
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break;
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case R_INTR_EN:
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case R_INTR_DIS:
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case R_TX_DATA:
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mask = 0;
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break;
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case R_RX_DATA:
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rx_data_bytes(s, &ret, s->num_txrx_bytes);
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DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
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xilinx_spips_update_ixr(s);
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return ret;
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}
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DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, s->regs[addr] & mask);
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return s->regs[addr] & mask;
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}
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static inline void tx_data_bytes(XilinxSPIPS *s, uint32_t value, int num)
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{
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int i;
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for (i = 0; i < num && !fifo8_is_full(&s->tx_fifo); ++i) {
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if (s->regs[R_CONFIG] & ENDIAN) {
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fifo8_push(&s->tx_fifo, (uint8_t)(value >> 24));
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value <<= 8;
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} else {
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fifo8_push(&s->tx_fifo, (uint8_t)value);
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value >>= 8;
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}
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}
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}
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static void xilinx_spips_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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int mask = ~0;
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int man_start_com = 0;
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XilinxSPIPS *s = opaque;
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DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value);
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addr >>= 2;
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switch (addr) {
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case R_CONFIG:
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mask = 0x0002FFFF;
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if (value & MAN_START_COM) {
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man_start_com = 1;
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}
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break;
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case R_INTR_STATUS:
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mask = IXR_ALL;
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s->regs[R_INTR_STATUS] &= ~(mask & value);
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goto no_reg_update;
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case R_INTR_DIS:
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mask = IXR_ALL;
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s->regs[R_INTR_MASK] &= ~(mask & value);
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goto no_reg_update;
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case R_INTR_EN:
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mask = IXR_ALL;
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s->regs[R_INTR_MASK] |= mask & value;
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goto no_reg_update;
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case R_EN:
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mask = 0x1;
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break;
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case R_SLAVE_IDLE_COUNT:
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mask = 0xFF;
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break;
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case R_RX_DATA:
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case R_INTR_MASK:
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case R_MOD_ID:
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mask = 0;
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break;
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case R_TX_DATA:
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tx_data_bytes(s, (uint32_t)value, s->num_txrx_bytes);
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goto no_reg_update;
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case R_TXD1:
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tx_data_bytes(s, (uint32_t)value, 1);
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goto no_reg_update;
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case R_TXD2:
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tx_data_bytes(s, (uint32_t)value, 2);
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goto no_reg_update;
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case R_TXD3:
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tx_data_bytes(s, (uint32_t)value, 3);
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goto no_reg_update;
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}
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s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask);
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no_reg_update:
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if (man_start_com) {
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xilinx_spips_flush_txfifo(s);
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}
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xilinx_spips_update_ixr(s);
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xilinx_spips_update_cs_lines(s);
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}
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static const MemoryRegionOps spips_ops = {
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.read = xilinx_spips_read,
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.write = xilinx_spips_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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#define LQSPI_CACHE_SIZE 1024
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static uint64_t
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lqspi_read(void *opaque, hwaddr addr, unsigned int size)
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{
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int i;
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XilinxSPIPS *s = opaque;
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if (addr >= s->lqspi_cached_addr &&
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addr <= s->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) {
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return s->lqspi_buf[(addr - s->lqspi_cached_addr) >> 2];
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} else {
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int flash_addr = (addr / num_effective_busses(s));
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int slave = flash_addr >> LQSPI_ADDRESS_BITS;
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int cache_entry = 0;
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DB_PRINT("config reg status: %08x\n", s->regs[R_LQSPI_CFG]);
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fifo8_reset(&s->tx_fifo);
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fifo8_reset(&s->rx_fifo);
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s->regs[R_CONFIG] &= ~CS;
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s->regs[R_CONFIG] |= (~(1 << slave) << CS_SHIFT) & CS;
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xilinx_spips_update_cs_lines(s);
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/* instruction */
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DB_PRINT("pushing read instruction: %02x\n",
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(uint8_t)(s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE));
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fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE);
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/* read address */
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DB_PRINT("pushing read address %06x\n", flash_addr);
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fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16));
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fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8));
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fifo8_push(&s->tx_fifo, (uint8_t)flash_addr);
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/* mode bits */
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if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) {
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fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG],
|
|
LQSPI_CFG_MODE_SHIFT,
|
|
LQSPI_CFG_MODE_WIDTH));
|
|
}
|
|
/* dummy bytes */
|
|
for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT,
|
|
LQSPI_CFG_DUMMY_WIDTH)); ++i) {
|
|
DB_PRINT("pushing dummy byte\n");
|
|
fifo8_push(&s->tx_fifo, 0);
|
|
}
|
|
xilinx_spips_flush_txfifo(s);
|
|
fifo8_reset(&s->rx_fifo);
|
|
|
|
DB_PRINT("starting QSPI data read\n");
|
|
|
|
for (i = 0; i < LQSPI_CACHE_SIZE / 4; ++i) {
|
|
tx_data_bytes(s, 0, 4);
|
|
xilinx_spips_flush_txfifo(s);
|
|
rx_data_bytes(s, &s->lqspi_buf[cache_entry], 4);
|
|
cache_entry++;
|
|
}
|
|
|
|
s->regs[R_CONFIG] |= CS;
|
|
xilinx_spips_update_cs_lines(s);
|
|
|
|
s->lqspi_cached_addr = addr;
|
|
return lqspi_read(opaque, addr, size);
|
|
}
|
|
}
|
|
|
|
static const MemoryRegionOps lqspi_ops = {
|
|
.read = lqspi_read,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
.valid = {
|
|
.min_access_size = 4,
|
|
.max_access_size = 4
|
|
}
|
|
};
|
|
|
|
static void xilinx_spips_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
XilinxSPIPS *s = XILINX_SPIPS(dev);
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
|
|
int i;
|
|
|
|
DB_PRINT("inited device model\n");
|
|
|
|
s->spi = g_new(SSIBus *, s->num_busses);
|
|
for (i = 0; i < s->num_busses; ++i) {
|
|
char bus_name[16];
|
|
snprintf(bus_name, 16, "spi%d", i);
|
|
s->spi[i] = ssi_create_bus(dev, bus_name);
|
|
}
|
|
|
|
s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses);
|
|
ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[0]);
|
|
ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[1]);
|
|
sysbus_init_irq(sbd, &s->irq);
|
|
for (i = 0; i < s->num_cs * s->num_busses; ++i) {
|
|
sysbus_init_irq(sbd, &s->cs_lines[i]);
|
|
}
|
|
|
|
memory_region_init_io(&s->iomem, &spips_ops, s, "spi", R_MAX*4);
|
|
sysbus_init_mmio(sbd, &s->iomem);
|
|
|
|
memory_region_init_io(&s->mmlqspi, &lqspi_ops, s, "lqspi",
|
|
(1 << LQSPI_ADDRESS_BITS) * 2);
|
|
sysbus_init_mmio(sbd, &s->mmlqspi);
|
|
|
|
s->irqline = -1;
|
|
s->lqspi_cached_addr = ~0ULL;
|
|
|
|
fifo8_create(&s->rx_fifo, RXFF_A);
|
|
fifo8_create(&s->tx_fifo, TXFF_A);
|
|
}
|
|
|
|
static int xilinx_spips_post_load(void *opaque, int version_id)
|
|
{
|
|
xilinx_spips_update_ixr((XilinxSPIPS *)opaque);
|
|
xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque);
|
|
return 0;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_xilinx_spips = {
|
|
.name = "xilinx_spips",
|
|
.version_id = 2,
|
|
.minimum_version_id = 2,
|
|
.minimum_version_id_old = 2,
|
|
.post_load = xilinx_spips_post_load,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_FIFO8(tx_fifo, XilinxSPIPS),
|
|
VMSTATE_FIFO8(rx_fifo, XilinxSPIPS),
|
|
VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, R_MAX),
|
|
VMSTATE_UINT8(snoop_state, XilinxSPIPS),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static Property xilinx_spips_properties[] = {
|
|
DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1),
|
|
DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4),
|
|
DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
static void xilinx_spips_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->realize = xilinx_spips_realize;
|
|
dc->reset = xilinx_spips_reset;
|
|
dc->props = xilinx_spips_properties;
|
|
dc->vmsd = &vmstate_xilinx_spips;
|
|
}
|
|
|
|
static const TypeInfo xilinx_spips_info = {
|
|
.name = TYPE_XILINX_SPIPS,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(XilinxSPIPS),
|
|
.class_init = xilinx_spips_class_init,
|
|
};
|
|
|
|
static void xilinx_spips_register_types(void)
|
|
{
|
|
type_register_static(&xilinx_spips_info);
|
|
}
|
|
|
|
type_init(xilinx_spips_register_types)
|