564b2040a6
Direct block chaining is documented here https://qemu.readthedocs.io/en/latest/devel/tcg.html#direct-block-chaining Hexagon inner loops end with the endloop0 instruction To go back to the beginning of the loop, this instructions writes to PC from register SA0 (start address 0). To use direct block chaining, we have to assign PC with a constant value. So, we specialize the code generation when the start of the translation block is equal to SA0. When this is the case, we defer the compare/branch from endloop0 to gen_end_tb. When this is done, we can assign the start address of the TB to PC. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20221108162906.3166-12-tsimpson@quicinc.com>
165 lines
5.1 KiB
C
165 lines
5.1 KiB
C
/*
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* Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HEXAGON_TRANSLATE_H
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#define HEXAGON_TRANSLATE_H
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#include "qemu/bitmap.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "exec/translator.h"
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#include "tcg/tcg-op.h"
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#include "insn.h"
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#include "internal.h"
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typedef struct DisasContext {
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DisasContextBase base;
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Packet *pkt;
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Insn *insn;
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uint32_t next_PC;
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uint32_t mem_idx;
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uint32_t num_packets;
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uint32_t num_insns;
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uint32_t num_hvx_insns;
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int reg_log[REG_WRITES_MAX];
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int reg_log_idx;
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DECLARE_BITMAP(regs_written, TOTAL_PER_THREAD_REGS);
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int preg_log[PRED_WRITES_MAX];
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int preg_log_idx;
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DECLARE_BITMAP(pregs_written, NUM_PREGS);
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uint8_t store_width[STORES_MAX];
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bool s1_store_processed;
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int future_vregs_idx;
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int future_vregs_num[VECTOR_TEMPS_MAX];
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int tmp_vregs_idx;
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int tmp_vregs_num[VECTOR_TEMPS_MAX];
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int vreg_log[NUM_VREGS];
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bool vreg_is_predicated[NUM_VREGS];
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int vreg_log_idx;
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DECLARE_BITMAP(vregs_updated_tmp, NUM_VREGS);
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DECLARE_BITMAP(vregs_updated, NUM_VREGS);
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DECLARE_BITMAP(vregs_select, NUM_VREGS);
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int qreg_log[NUM_QREGS];
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bool qreg_is_predicated[NUM_QREGS];
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int qreg_log_idx;
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bool pre_commit;
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TCGCond branch_cond;
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target_ulong branch_dest;
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bool is_tight_loop;
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} DisasContext;
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static inline void ctx_log_reg_write(DisasContext *ctx, int rnum)
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{
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if (test_bit(rnum, ctx->regs_written)) {
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HEX_DEBUG_LOG("WARNING: Multiple writes to r%d\n", rnum);
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}
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ctx->reg_log[ctx->reg_log_idx] = rnum;
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ctx->reg_log_idx++;
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set_bit(rnum, ctx->regs_written);
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}
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static inline void ctx_log_reg_write_pair(DisasContext *ctx, int rnum)
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{
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ctx_log_reg_write(ctx, rnum);
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ctx_log_reg_write(ctx, rnum + 1);
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}
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static inline void ctx_log_pred_write(DisasContext *ctx, int pnum)
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{
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ctx->preg_log[ctx->preg_log_idx] = pnum;
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ctx->preg_log_idx++;
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set_bit(pnum, ctx->pregs_written);
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}
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static inline bool is_preloaded(DisasContext *ctx, int num)
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{
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return test_bit(num, ctx->regs_written);
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}
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static inline bool is_vreg_preloaded(DisasContext *ctx, int num)
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{
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return test_bit(num, ctx->vregs_updated) ||
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test_bit(num, ctx->vregs_updated_tmp);
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}
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intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum,
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int num, bool alloc_ok);
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intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum,
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int num, bool alloc_ok);
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static inline void ctx_log_vreg_write(DisasContext *ctx,
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int rnum, VRegWriteType type,
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bool is_predicated)
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{
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if (type != EXT_TMP) {
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ctx->vreg_log[ctx->vreg_log_idx] = rnum;
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ctx->vreg_is_predicated[ctx->vreg_log_idx] = is_predicated;
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ctx->vreg_log_idx++;
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set_bit(rnum, ctx->vregs_updated);
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}
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if (type == EXT_NEW) {
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set_bit(rnum, ctx->vregs_select);
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}
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if (type == EXT_TMP) {
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set_bit(rnum, ctx->vregs_updated_tmp);
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}
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}
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static inline void ctx_log_vreg_write_pair(DisasContext *ctx,
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int rnum, VRegWriteType type,
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bool is_predicated)
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{
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ctx_log_vreg_write(ctx, rnum ^ 0, type, is_predicated);
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ctx_log_vreg_write(ctx, rnum ^ 1, type, is_predicated);
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}
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static inline void ctx_log_qreg_write(DisasContext *ctx,
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int rnum, bool is_predicated)
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{
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ctx->qreg_log[ctx->qreg_log_idx] = rnum;
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ctx->qreg_is_predicated[ctx->qreg_log_idx] = is_predicated;
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ctx->qreg_log_idx++;
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}
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extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS];
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extern TCGv hex_pred[NUM_PREGS];
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extern TCGv hex_this_PC;
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extern TCGv hex_slot_cancelled;
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extern TCGv hex_branch_taken;
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extern TCGv hex_new_value[TOTAL_PER_THREAD_REGS];
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extern TCGv hex_reg_written[TOTAL_PER_THREAD_REGS];
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extern TCGv hex_new_pred_value[NUM_PREGS];
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extern TCGv hex_pred_written;
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extern TCGv hex_store_addr[STORES_MAX];
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extern TCGv hex_store_width[STORES_MAX];
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extern TCGv hex_store_val32[STORES_MAX];
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extern TCGv_i64 hex_store_val64[STORES_MAX];
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extern TCGv hex_dczero_addr;
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extern TCGv hex_llsc_addr;
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extern TCGv hex_llsc_val;
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extern TCGv_i64 hex_llsc_val_i64;
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extern TCGv hex_VRegs_updated;
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extern TCGv hex_QRegs_updated;
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extern TCGv hex_vstore_addr[VSTORES_MAX];
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extern TCGv hex_vstore_size[VSTORES_MAX];
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extern TCGv hex_vstore_pending[VSTORES_MAX];
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bool is_gather_store_insn(DisasContext *ctx);
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void process_store(DisasContext *ctx, int slot_num);
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#endif
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