452fcdbc49
This cleanup makes the number of objects depending on qapi/qmp/qdict.h drop from 4550 (out of 4743) to 368 in my "build everything" tree. For qapi/qmp/qobject.h, the number drops from 4552 to 390. While there, separate #include from file comment with a blank line. Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20180201111846.21846-13-armbru@redhat.com>
664 lines
23 KiB
C
664 lines
23 KiB
C
/*
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* QEMU monitor
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "monitor/monitor.h"
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#include "monitor/hmp-target.h"
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#include "qapi/qmp/qdict.h"
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#include "hw/i386/pc.h"
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#include "sysemu/kvm.h"
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#include "hmp.h"
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static void print_pte(Monitor *mon, CPUArchState *env, hwaddr addr,
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hwaddr pte, hwaddr mask)
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{
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#ifdef TARGET_X86_64
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if (env->cr[4] & CR4_LA57_MASK) {
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if (addr & (1ULL << 56)) {
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addr |= -1LL << 57;
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}
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} else {
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if (addr & (1ULL << 47)) {
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addr |= -1LL << 48;
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}
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}
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#endif
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monitor_printf(mon, TARGET_FMT_plx ": " TARGET_FMT_plx
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" %c%c%c%c%c%c%c%c%c\n",
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addr,
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pte & mask,
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pte & PG_NX_MASK ? 'X' : '-',
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pte & PG_GLOBAL_MASK ? 'G' : '-',
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pte & PG_PSE_MASK ? 'P' : '-',
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pte & PG_DIRTY_MASK ? 'D' : '-',
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pte & PG_ACCESSED_MASK ? 'A' : '-',
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pte & PG_PCD_MASK ? 'C' : '-',
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pte & PG_PWT_MASK ? 'T' : '-',
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pte & PG_USER_MASK ? 'U' : '-',
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pte & PG_RW_MASK ? 'W' : '-');
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}
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static void tlb_info_32(Monitor *mon, CPUArchState *env)
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{
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unsigned int l1, l2;
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uint32_t pgd, pde, pte;
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pgd = env->cr[3] & ~0xfff;
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for(l1 = 0; l1 < 1024; l1++) {
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cpu_physical_memory_read(pgd + l1 * 4, &pde, 4);
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pde = le32_to_cpu(pde);
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if (pde & PG_PRESENT_MASK) {
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if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
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/* 4M pages */
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print_pte(mon, env, (l1 << 22), pde, ~((1 << 21) - 1));
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} else {
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for(l2 = 0; l2 < 1024; l2++) {
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cpu_physical_memory_read((pde & ~0xfff) + l2 * 4, &pte, 4);
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pte = le32_to_cpu(pte);
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if (pte & PG_PRESENT_MASK) {
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print_pte(mon, env, (l1 << 22) + (l2 << 12),
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pte & ~PG_PSE_MASK,
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~0xfff);
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}
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}
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}
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}
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}
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}
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static void tlb_info_pae32(Monitor *mon, CPUArchState *env)
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{
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unsigned int l1, l2, l3;
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uint64_t pdpe, pde, pte;
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uint64_t pdp_addr, pd_addr, pt_addr;
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pdp_addr = env->cr[3] & ~0x1f;
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for (l1 = 0; l1 < 4; l1++) {
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cpu_physical_memory_read(pdp_addr + l1 * 8, &pdpe, 8);
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pdpe = le64_to_cpu(pdpe);
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if (pdpe & PG_PRESENT_MASK) {
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pd_addr = pdpe & 0x3fffffffff000ULL;
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for (l2 = 0; l2 < 512; l2++) {
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cpu_physical_memory_read(pd_addr + l2 * 8, &pde, 8);
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pde = le64_to_cpu(pde);
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if (pde & PG_PRESENT_MASK) {
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if (pde & PG_PSE_MASK) {
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/* 2M pages with PAE, CR4.PSE is ignored */
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print_pte(mon, env, (l1 << 30) + (l2 << 21), pde,
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~((hwaddr)(1 << 20) - 1));
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} else {
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pt_addr = pde & 0x3fffffffff000ULL;
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for (l3 = 0; l3 < 512; l3++) {
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cpu_physical_memory_read(pt_addr + l3 * 8, &pte, 8);
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pte = le64_to_cpu(pte);
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if (pte & PG_PRESENT_MASK) {
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print_pte(mon, env, (l1 << 30) + (l2 << 21)
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+ (l3 << 12),
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pte & ~PG_PSE_MASK,
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~(hwaddr)0xfff);
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}
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}
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}
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}
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}
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}
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}
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}
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#ifdef TARGET_X86_64
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static void tlb_info_la48(Monitor *mon, CPUArchState *env,
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uint64_t l0, uint64_t pml4_addr)
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{
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uint64_t l1, l2, l3, l4;
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uint64_t pml4e, pdpe, pde, pte;
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uint64_t pdp_addr, pd_addr, pt_addr;
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for (l1 = 0; l1 < 512; l1++) {
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cpu_physical_memory_read(pml4_addr + l1 * 8, &pml4e, 8);
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pml4e = le64_to_cpu(pml4e);
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if (!(pml4e & PG_PRESENT_MASK)) {
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continue;
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}
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pdp_addr = pml4e & 0x3fffffffff000ULL;
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for (l2 = 0; l2 < 512; l2++) {
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cpu_physical_memory_read(pdp_addr + l2 * 8, &pdpe, 8);
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pdpe = le64_to_cpu(pdpe);
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if (!(pdpe & PG_PRESENT_MASK)) {
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continue;
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}
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if (pdpe & PG_PSE_MASK) {
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/* 1G pages, CR4.PSE is ignored */
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print_pte(mon, env, (l0 << 48) + (l1 << 39) + (l2 << 30),
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pdpe, 0x3ffffc0000000ULL);
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continue;
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}
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pd_addr = pdpe & 0x3fffffffff000ULL;
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for (l3 = 0; l3 < 512; l3++) {
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cpu_physical_memory_read(pd_addr + l3 * 8, &pde, 8);
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pde = le64_to_cpu(pde);
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if (!(pde & PG_PRESENT_MASK)) {
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continue;
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}
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if (pde & PG_PSE_MASK) {
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/* 2M pages, CR4.PSE is ignored */
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print_pte(mon, env, (l0 << 48) + (l1 << 39) + (l2 << 30) +
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(l3 << 21), pde, 0x3ffffffe00000ULL);
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continue;
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}
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pt_addr = pde & 0x3fffffffff000ULL;
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for (l4 = 0; l4 < 512; l4++) {
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cpu_physical_memory_read(pt_addr
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+ l4 * 8,
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&pte, 8);
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pte = le64_to_cpu(pte);
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if (pte & PG_PRESENT_MASK) {
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print_pte(mon, env, (l0 << 48) + (l1 << 39) +
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(l2 << 30) + (l3 << 21) + (l4 << 12),
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pte & ~PG_PSE_MASK, 0x3fffffffff000ULL);
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}
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}
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}
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}
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}
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}
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static void tlb_info_la57(Monitor *mon, CPUArchState *env)
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{
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uint64_t l0;
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uint64_t pml5e;
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uint64_t pml5_addr;
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pml5_addr = env->cr[3] & 0x3fffffffff000ULL;
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for (l0 = 0; l0 < 512; l0++) {
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cpu_physical_memory_read(pml5_addr + l0 * 8, &pml5e, 8);
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pml5e = le64_to_cpu(pml5e);
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if (pml5e & PG_PRESENT_MASK) {
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tlb_info_la48(mon, env, l0, pml5e & 0x3fffffffff000ULL);
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}
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}
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}
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#endif /* TARGET_X86_64 */
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void hmp_info_tlb(Monitor *mon, const QDict *qdict)
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{
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CPUArchState *env;
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env = mon_get_cpu_env();
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if (!env) {
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monitor_printf(mon, "No CPU available\n");
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return;
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}
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if (!(env->cr[0] & CR0_PG_MASK)) {
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monitor_printf(mon, "PG disabled\n");
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return;
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}
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if (env->cr[4] & CR4_PAE_MASK) {
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#ifdef TARGET_X86_64
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if (env->hflags & HF_LMA_MASK) {
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if (env->cr[4] & CR4_LA57_MASK) {
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tlb_info_la57(mon, env);
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} else {
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tlb_info_la48(mon, env, 0, env->cr[3] & 0x3fffffffff000ULL);
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}
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} else
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#endif
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{
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tlb_info_pae32(mon, env);
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}
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} else {
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tlb_info_32(mon, env);
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}
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}
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static void mem_print(Monitor *mon, hwaddr *pstart,
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int *plast_prot,
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hwaddr end, int prot)
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{
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int prot1;
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prot1 = *plast_prot;
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if (prot != prot1) {
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if (*pstart != -1) {
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monitor_printf(mon, TARGET_FMT_plx "-" TARGET_FMT_plx " "
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TARGET_FMT_plx " %c%c%c\n",
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*pstart, end, end - *pstart,
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prot1 & PG_USER_MASK ? 'u' : '-',
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'r',
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prot1 & PG_RW_MASK ? 'w' : '-');
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}
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if (prot != 0)
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*pstart = end;
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else
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*pstart = -1;
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*plast_prot = prot;
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}
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}
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static void mem_info_32(Monitor *mon, CPUArchState *env)
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{
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unsigned int l1, l2;
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int prot, last_prot;
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uint32_t pgd, pde, pte;
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hwaddr start, end;
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pgd = env->cr[3] & ~0xfff;
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last_prot = 0;
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start = -1;
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for(l1 = 0; l1 < 1024; l1++) {
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cpu_physical_memory_read(pgd + l1 * 4, &pde, 4);
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pde = le32_to_cpu(pde);
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end = l1 << 22;
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if (pde & PG_PRESENT_MASK) {
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if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
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prot = pde & (PG_USER_MASK | PG_RW_MASK | PG_PRESENT_MASK);
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mem_print(mon, &start, &last_prot, end, prot);
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} else {
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for(l2 = 0; l2 < 1024; l2++) {
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cpu_physical_memory_read((pde & ~0xfff) + l2 * 4, &pte, 4);
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pte = le32_to_cpu(pte);
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end = (l1 << 22) + (l2 << 12);
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if (pte & PG_PRESENT_MASK) {
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prot = pte & pde &
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(PG_USER_MASK | PG_RW_MASK | PG_PRESENT_MASK);
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} else {
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prot = 0;
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}
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mem_print(mon, &start, &last_prot, end, prot);
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}
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}
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} else {
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prot = 0;
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mem_print(mon, &start, &last_prot, end, prot);
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}
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}
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/* Flush last range */
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mem_print(mon, &start, &last_prot, (hwaddr)1 << 32, 0);
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}
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static void mem_info_pae32(Monitor *mon, CPUArchState *env)
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{
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unsigned int l1, l2, l3;
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int prot, last_prot;
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uint64_t pdpe, pde, pte;
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uint64_t pdp_addr, pd_addr, pt_addr;
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hwaddr start, end;
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pdp_addr = env->cr[3] & ~0x1f;
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last_prot = 0;
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start = -1;
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for (l1 = 0; l1 < 4; l1++) {
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cpu_physical_memory_read(pdp_addr + l1 * 8, &pdpe, 8);
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pdpe = le64_to_cpu(pdpe);
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end = l1 << 30;
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if (pdpe & PG_PRESENT_MASK) {
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pd_addr = pdpe & 0x3fffffffff000ULL;
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for (l2 = 0; l2 < 512; l2++) {
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cpu_physical_memory_read(pd_addr + l2 * 8, &pde, 8);
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pde = le64_to_cpu(pde);
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end = (l1 << 30) + (l2 << 21);
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if (pde & PG_PRESENT_MASK) {
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if (pde & PG_PSE_MASK) {
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prot = pde & (PG_USER_MASK | PG_RW_MASK |
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PG_PRESENT_MASK);
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mem_print(mon, &start, &last_prot, end, prot);
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} else {
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pt_addr = pde & 0x3fffffffff000ULL;
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for (l3 = 0; l3 < 512; l3++) {
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cpu_physical_memory_read(pt_addr + l3 * 8, &pte, 8);
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pte = le64_to_cpu(pte);
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end = (l1 << 30) + (l2 << 21) + (l3 << 12);
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if (pte & PG_PRESENT_MASK) {
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prot = pte & pde & (PG_USER_MASK | PG_RW_MASK |
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PG_PRESENT_MASK);
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} else {
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prot = 0;
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}
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mem_print(mon, &start, &last_prot, end, prot);
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}
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}
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} else {
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prot = 0;
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mem_print(mon, &start, &last_prot, end, prot);
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}
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}
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} else {
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prot = 0;
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mem_print(mon, &start, &last_prot, end, prot);
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}
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}
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/* Flush last range */
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mem_print(mon, &start, &last_prot, (hwaddr)1 << 32, 0);
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}
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#ifdef TARGET_X86_64
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static void mem_info_la48(Monitor *mon, CPUArchState *env)
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{
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int prot, last_prot;
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uint64_t l1, l2, l3, l4;
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uint64_t pml4e, pdpe, pde, pte;
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uint64_t pml4_addr, pdp_addr, pd_addr, pt_addr, start, end;
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pml4_addr = env->cr[3] & 0x3fffffffff000ULL;
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last_prot = 0;
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start = -1;
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for (l1 = 0; l1 < 512; l1++) {
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cpu_physical_memory_read(pml4_addr + l1 * 8, &pml4e, 8);
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pml4e = le64_to_cpu(pml4e);
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end = l1 << 39;
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if (pml4e & PG_PRESENT_MASK) {
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pdp_addr = pml4e & 0x3fffffffff000ULL;
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for (l2 = 0; l2 < 512; l2++) {
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cpu_physical_memory_read(pdp_addr + l2 * 8, &pdpe, 8);
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pdpe = le64_to_cpu(pdpe);
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end = (l1 << 39) + (l2 << 30);
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if (pdpe & PG_PRESENT_MASK) {
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if (pdpe & PG_PSE_MASK) {
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prot = pdpe & (PG_USER_MASK | PG_RW_MASK |
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PG_PRESENT_MASK);
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prot &= pml4e;
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mem_print(mon, &start, &last_prot, end, prot);
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} else {
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pd_addr = pdpe & 0x3fffffffff000ULL;
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for (l3 = 0; l3 < 512; l3++) {
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cpu_physical_memory_read(pd_addr + l3 * 8, &pde, 8);
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pde = le64_to_cpu(pde);
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end = (l1 << 39) + (l2 << 30) + (l3 << 21);
|
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if (pde & PG_PRESENT_MASK) {
|
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if (pde & PG_PSE_MASK) {
|
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prot = pde & (PG_USER_MASK | PG_RW_MASK |
|
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PG_PRESENT_MASK);
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prot &= pml4e & pdpe;
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mem_print(mon, &start, &last_prot, end, prot);
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} else {
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pt_addr = pde & 0x3fffffffff000ULL;
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for (l4 = 0; l4 < 512; l4++) {
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cpu_physical_memory_read(pt_addr
|
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+ l4 * 8,
|
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&pte, 8);
|
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pte = le64_to_cpu(pte);
|
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end = (l1 << 39) + (l2 << 30) +
|
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(l3 << 21) + (l4 << 12);
|
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if (pte & PG_PRESENT_MASK) {
|
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prot = pte & (PG_USER_MASK | PG_RW_MASK |
|
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PG_PRESENT_MASK);
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prot &= pml4e & pdpe & pde;
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} else {
|
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prot = 0;
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}
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mem_print(mon, &start, &last_prot, end, prot);
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}
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}
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} else {
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prot = 0;
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mem_print(mon, &start, &last_prot, end, prot);
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}
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}
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}
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} else {
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prot = 0;
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mem_print(mon, &start, &last_prot, end, prot);
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}
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}
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} else {
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prot = 0;
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mem_print(mon, &start, &last_prot, end, prot);
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}
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}
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/* Flush last range */
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mem_print(mon, &start, &last_prot, (hwaddr)1 << 48, 0);
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}
|
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|
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static void mem_info_la57(Monitor *mon, CPUArchState *env)
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{
|
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int prot, last_prot;
|
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uint64_t l0, l1, l2, l3, l4;
|
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uint64_t pml5e, pml4e, pdpe, pde, pte;
|
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uint64_t pml5_addr, pml4_addr, pdp_addr, pd_addr, pt_addr, start, end;
|
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|
|
pml5_addr = env->cr[3] & 0x3fffffffff000ULL;
|
|
last_prot = 0;
|
|
start = -1;
|
|
for (l0 = 0; l0 < 512; l0++) {
|
|
cpu_physical_memory_read(pml5_addr + l0 * 8, &pml5e, 8);
|
|
pml5e = le64_to_cpu(pml5e);
|
|
end = l0 << 48;
|
|
if (!(pml5e & PG_PRESENT_MASK)) {
|
|
prot = 0;
|
|
mem_print(mon, &start, &last_prot, end, prot);
|
|
continue;
|
|
}
|
|
|
|
pml4_addr = pml5e & 0x3fffffffff000ULL;
|
|
for (l1 = 0; l1 < 512; l1++) {
|
|
cpu_physical_memory_read(pml4_addr + l1 * 8, &pml4e, 8);
|
|
pml4e = le64_to_cpu(pml4e);
|
|
end = (l0 << 48) + (l1 << 39);
|
|
if (!(pml4e & PG_PRESENT_MASK)) {
|
|
prot = 0;
|
|
mem_print(mon, &start, &last_prot, end, prot);
|
|
continue;
|
|
}
|
|
|
|
pdp_addr = pml4e & 0x3fffffffff000ULL;
|
|
for (l2 = 0; l2 < 512; l2++) {
|
|
cpu_physical_memory_read(pdp_addr + l2 * 8, &pdpe, 8);
|
|
pdpe = le64_to_cpu(pdpe);
|
|
end = (l0 << 48) + (l1 << 39) + (l2 << 30);
|
|
if (pdpe & PG_PRESENT_MASK) {
|
|
prot = 0;
|
|
mem_print(mon, &start, &last_prot, end, prot);
|
|
continue;
|
|
}
|
|
|
|
if (pdpe & PG_PSE_MASK) {
|
|
prot = pdpe & (PG_USER_MASK | PG_RW_MASK |
|
|
PG_PRESENT_MASK);
|
|
prot &= pml5e & pml4e;
|
|
mem_print(mon, &start, &last_prot, end, prot);
|
|
continue;
|
|
}
|
|
|
|
pd_addr = pdpe & 0x3fffffffff000ULL;
|
|
for (l3 = 0; l3 < 512; l3++) {
|
|
cpu_physical_memory_read(pd_addr + l3 * 8, &pde, 8);
|
|
pde = le64_to_cpu(pde);
|
|
end = (l0 << 48) + (l1 << 39) + (l2 << 30) + (l3 << 21);
|
|
if (pde & PG_PRESENT_MASK) {
|
|
prot = 0;
|
|
mem_print(mon, &start, &last_prot, end, prot);
|
|
continue;
|
|
}
|
|
|
|
if (pde & PG_PSE_MASK) {
|
|
prot = pde & (PG_USER_MASK | PG_RW_MASK |
|
|
PG_PRESENT_MASK);
|
|
prot &= pml5e & pml4e & pdpe;
|
|
mem_print(mon, &start, &last_prot, end, prot);
|
|
continue;
|
|
}
|
|
|
|
pt_addr = pde & 0x3fffffffff000ULL;
|
|
for (l4 = 0; l4 < 512; l4++) {
|
|
cpu_physical_memory_read(pt_addr + l4 * 8, &pte, 8);
|
|
pte = le64_to_cpu(pte);
|
|
end = (l0 << 48) + (l1 << 39) + (l2 << 30) +
|
|
(l3 << 21) + (l4 << 12);
|
|
if (pte & PG_PRESENT_MASK) {
|
|
prot = pte & (PG_USER_MASK | PG_RW_MASK |
|
|
PG_PRESENT_MASK);
|
|
prot &= pml5e & pml4e & pdpe & pde;
|
|
} else {
|
|
prot = 0;
|
|
}
|
|
mem_print(mon, &start, &last_prot, end, prot);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/* Flush last range */
|
|
mem_print(mon, &start, &last_prot, (hwaddr)1 << 57, 0);
|
|
}
|
|
#endif /* TARGET_X86_64 */
|
|
|
|
void hmp_info_mem(Monitor *mon, const QDict *qdict)
|
|
{
|
|
CPUArchState *env;
|
|
|
|
env = mon_get_cpu_env();
|
|
if (!env) {
|
|
monitor_printf(mon, "No CPU available\n");
|
|
return;
|
|
}
|
|
|
|
if (!(env->cr[0] & CR0_PG_MASK)) {
|
|
monitor_printf(mon, "PG disabled\n");
|
|
return;
|
|
}
|
|
if (env->cr[4] & CR4_PAE_MASK) {
|
|
#ifdef TARGET_X86_64
|
|
if (env->hflags & HF_LMA_MASK) {
|
|
if (env->cr[4] & CR4_LA57_MASK) {
|
|
mem_info_la57(mon, env);
|
|
} else {
|
|
mem_info_la48(mon, env);
|
|
}
|
|
} else
|
|
#endif
|
|
{
|
|
mem_info_pae32(mon, env);
|
|
}
|
|
} else {
|
|
mem_info_32(mon, env);
|
|
}
|
|
}
|
|
|
|
void hmp_mce(Monitor *mon, const QDict *qdict)
|
|
{
|
|
X86CPU *cpu;
|
|
CPUState *cs;
|
|
int cpu_index = qdict_get_int(qdict, "cpu_index");
|
|
int bank = qdict_get_int(qdict, "bank");
|
|
uint64_t status = qdict_get_int(qdict, "status");
|
|
uint64_t mcg_status = qdict_get_int(qdict, "mcg_status");
|
|
uint64_t addr = qdict_get_int(qdict, "addr");
|
|
uint64_t misc = qdict_get_int(qdict, "misc");
|
|
int flags = MCE_INJECT_UNCOND_AO;
|
|
|
|
if (qdict_get_try_bool(qdict, "broadcast", false)) {
|
|
flags |= MCE_INJECT_BROADCAST;
|
|
}
|
|
cs = qemu_get_cpu(cpu_index);
|
|
if (cs != NULL) {
|
|
cpu = X86_CPU(cs);
|
|
cpu_x86_inject_mce(mon, cpu, bank, status, mcg_status, addr, misc,
|
|
flags);
|
|
}
|
|
}
|
|
|
|
static target_long monitor_get_pc(const struct MonitorDef *md, int val)
|
|
{
|
|
CPUArchState *env = mon_get_cpu_env();
|
|
return env->eip + env->segs[R_CS].base;
|
|
}
|
|
|
|
const MonitorDef monitor_defs[] = {
|
|
#define SEG(name, seg) \
|
|
{ name, offsetof(CPUX86State, segs[seg].selector), NULL, MD_I32 },\
|
|
{ name ".base", offsetof(CPUX86State, segs[seg].base) },\
|
|
{ name ".limit", offsetof(CPUX86State, segs[seg].limit), NULL, MD_I32 },
|
|
|
|
{ "eax", offsetof(CPUX86State, regs[0]) },
|
|
{ "ecx", offsetof(CPUX86State, regs[1]) },
|
|
{ "edx", offsetof(CPUX86State, regs[2]) },
|
|
{ "ebx", offsetof(CPUX86State, regs[3]) },
|
|
{ "esp|sp", offsetof(CPUX86State, regs[4]) },
|
|
{ "ebp|fp", offsetof(CPUX86State, regs[5]) },
|
|
{ "esi", offsetof(CPUX86State, regs[6]) },
|
|
{ "edi", offsetof(CPUX86State, regs[7]) },
|
|
#ifdef TARGET_X86_64
|
|
{ "r8", offsetof(CPUX86State, regs[8]) },
|
|
{ "r9", offsetof(CPUX86State, regs[9]) },
|
|
{ "r10", offsetof(CPUX86State, regs[10]) },
|
|
{ "r11", offsetof(CPUX86State, regs[11]) },
|
|
{ "r12", offsetof(CPUX86State, regs[12]) },
|
|
{ "r13", offsetof(CPUX86State, regs[13]) },
|
|
{ "r14", offsetof(CPUX86State, regs[14]) },
|
|
{ "r15", offsetof(CPUX86State, regs[15]) },
|
|
#endif
|
|
{ "eflags", offsetof(CPUX86State, eflags) },
|
|
{ "eip", offsetof(CPUX86State, eip) },
|
|
SEG("cs", R_CS)
|
|
SEG("ds", R_DS)
|
|
SEG("es", R_ES)
|
|
SEG("ss", R_SS)
|
|
SEG("fs", R_FS)
|
|
SEG("gs", R_GS)
|
|
{ "pc", 0, monitor_get_pc, },
|
|
{ NULL },
|
|
};
|
|
|
|
const MonitorDef *target_monitor_defs(void)
|
|
{
|
|
return monitor_defs;
|
|
}
|
|
|
|
void hmp_info_local_apic(Monitor *mon, const QDict *qdict)
|
|
{
|
|
CPUState *cs;
|
|
|
|
if (qdict_haskey(qdict, "apic-id")) {
|
|
int id = qdict_get_try_int(qdict, "apic-id", 0);
|
|
cs = cpu_by_arch_id(id);
|
|
} else {
|
|
cs = mon_get_cpu();
|
|
}
|
|
|
|
|
|
if (!cs) {
|
|
monitor_printf(mon, "No CPU available\n");
|
|
return;
|
|
}
|
|
x86_cpu_dump_local_apic_state(cs, (FILE *)mon, monitor_fprintf,
|
|
CPU_DUMP_FPU);
|
|
}
|
|
|
|
void hmp_info_io_apic(Monitor *mon, const QDict *qdict)
|
|
{
|
|
if (kvm_irqchip_in_kernel() &&
|
|
!kvm_irqchip_is_split()) {
|
|
kvm_ioapic_dump_state(mon, qdict);
|
|
} else {
|
|
ioapic_dump_state(mon, qdict);
|
|
}
|
|
}
|