qemu-e2k/target/mips
Peter Maydell 20b42789aa target/mips/mxu_translate.c: Fix array overrun for D16MIN/D16MAX
Coverity reported (CID 1450831) an array overrun in
gen_mxu_D16MAX_D16MIN():

  1103     } else if (unlikely((XRb == 0) || (XRa == 0))) {
  ....
  1112         if (opc == OPC_MXU_D16MAX) {
  1113             tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1);
  1114         } else {
  1115             tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1);
  1116         }

>>> Overrunning array "mxu_gpr" of 15 8-byte elements at element
    index 4294967295 (byte offset 34359738367) using index "XRa - 1U"
    (which evaluates to 4294967295).

This happens because the code is confused about which of XRa, XRb and
XRc is the output, and which are the inputs.  XRa is the output, but
most of the conditions separating out different special cases are
written as if XRc is the output, with the result that we can end up
in the code path that assumes XRa is non-0 even when it is zero.

Fix the erroneous code, bringing it in to line with the structure
used in functions like gen_mxu_S32MAX_S32MIN() and
gen_mxu_Q8MAX_Q8MIN().

Fixes: CID 1450831
Fixes: bb84cbf385
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210316131353.4533-1-peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-03-22 15:05:41 +01:00
..
addr.c
cp0_helper.c
cp0_timer.c
cpu-defs.c.inc target/mips: Remove vendor specific CPU definitions 2021-01-14 17:13:54 +01:00
cpu-param.h
cpu-qom.h
cpu.c Testing, guest-loader and other misc tweaks 2021-03-11 16:20:58 +00:00
cpu.h target/mips: Promote 128-bit multimedia registers as global ones 2021-02-21 19:42:34 +01:00
dsp_helper.c
fpu_helper.c
fpu_helper.h
gdbstub.c
helper.h
internal.h target/mips: Let CPUMIPSTLBContext::map_address() take MMUAccessType 2021-02-21 19:42:34 +01:00
kvm_mips.h
kvm.c sysemu: Let VMChangeStateHandler take boolean 'running' argument 2021-03-09 23:13:57 +01:00
lmmi_helper.c
machine.c
meson.build target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree 2021-03-13 23:43:07 +01:00
mips32r6.decode target/mips: Convert Rel6 LL/SC opcodes to decodetree 2021-01-14 17:13:53 +01:00
mips64r6.decode
mips-defs.h target/mips: Remove vendor specific CPU definitions 2021-01-14 17:13:54 +01:00
mips-semi.c semihosting: Move include/hw/semihosting/ -> include/semihosting/ 2021-03-10 15:34:12 +00:00
msa32.decode
msa64.decode
msa_helper.c target/mips: Include missing "tcg/tcg.h" header 2021-02-21 19:42:34 +01:00
msa_helper.h.inc
msa_translate.c
mxu_translate.c target/mips/mxu_translate.c: Fix array overrun for D16MIN/D16MAX 2021-03-22 15:05:41 +01:00
op_helper.c target/mips: Let do_translate_address() take MMUAccessType argument 2021-02-21 19:42:34 +01:00
rel6_translate.c
tlb_helper.c target/mips: Remove unused 'rw' argument from page_table_walk_refill() 2021-02-21 19:42:34 +01:00
TODO
trace-events
trace.h
translate_addr_const.c
translate.c target/mips/tx79: Salvage instructions description comment 2021-03-13 23:43:30 +01:00
translate.h target/mips/translate: Make gen_rdhwr() public 2021-03-13 23:43:14 +01:00
tx79_translate.c target/mips/tx79: Salvage instructions description comment 2021-03-13 23:43:30 +01:00
tx79.decode target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree 2021-03-13 23:43:24 +01:00
txx9_translate.c target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree 2021-03-13 23:43:07 +01:00